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參數(shù)資料
| 型號(hào)： | MC68HC08LT8CFGE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44 |
| 文件頁(yè)數(shù)： | 89/156頁(yè) |
| 文件大?。?/td> | 1107K |
| 代理商： | MC68HC08LT8CFGE |
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System Integration Module (SIM)
MC68HC08LT8 Data Sheet, Rev. 1
38
Freescale Semiconductor
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
4.3 Reset and System Initialization
The MCU has these reset sources:
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 4.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). (See 4.7 SIM Registers.)
4.3.1 External Pin Reset
The RST pin circuit includes an internal pull-up device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset.
See Table 4-2 for details. Figure 4-4 shows the relative timing.
Figure 4-4. External Reset Timing
4.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see Figure 4-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI,
or POR (see Figure 4-6).
Table 4-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
RST
IAB
PC
VECT H VECT L
CGMXCLK
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