參數(shù)資料
型號： MC68HC08LT8CFGE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù)： 118/156頁
文件大小： 1107K
代理商： MC68HC08LT8CFGE
Timer Interface Module (TIM)
MC68HC08LT8 Data Sheet, Rev. 1
64
Freescale Semiconductor
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is
complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost
due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table
6-2 shows. Reset clears the PS[2:0] bits.
Table 6-2. Prescaler Selection
PS2
PS1
PS0
TIM Clock Source
0
Internal bus clock
÷ 1
0
1
Internal bus clock
÷ 2
0
1
0
Internal bus clock
÷ 4
0
1
Internal bus clock
÷ 8
1
0
Internal bus clock
÷ 16
1
0
1
Internal bus clock
÷ 32
1
0
Internal bus clock
÷ 64
1
Not available
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