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參數(shù)資料
| 型號： | MC68HC08LT8CFGE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44 |
| 文件頁數(shù)： | 27/156頁 |
| 文件大小： | 1107K |
| 代理商： | MC68HC08LT8CFGE |
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Low-Voltage Inhibit (LVI)
MC68HC08LT8 Data Sheet, Rev. 1
122
Freescale Semiconductor
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator.
Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI
reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage,
VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
The LVI trip point selection bits, LVISEL[1:0], select the trip point voltage, VTRIPF, to be configured for 5V
or 3V operation. The actual trip points are shown in Chapter 16 Electrical Specifications.
Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever the LVIOUT bit toggles (from logic
0 to logic 1, or from logic 1 to logic 0).
NOTE
After a power-on reset (POR) the LVI’s default mode of operation is 3V.
If a 5V system is used, the user must modified the LVISEL[1:0] bits to raise
the trip point to 5V operation. Note that this must be done after every
power-on reset since the default will revert back to 3V mode after each
power-on reset. If the VDD supply is below the 3V mode trip voltage when
POR is released, the MCU will immediately go into reset. The LVI in this
case will hold the MCU in reset until either VDD goes above the rising 3V
trip point, VTRIPR, which will release reset or VDD decreases to
approximately 0V which will re-trigger the power-on reset.
LVISTOP, LVIPWRD, LVIRSTD, and LVISEL[1:0] are in the configuration registers. See Section 5.
Configuration Registers (CONFIG) for details of the LVI’s configuration bits. Once an LVI reset occurs,
the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset.
See 4.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). The
LVIIE, LVIIF, and LVIIACK bits in the LVISR control LVI interrupt functions.
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
13.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling
the LVIOUT bit, or by setting the LVI interrupt enable bit, LVIIE, to enable interrupt requests. In the
configuration register 1 (CONFIG1), the LVIPWRD bit must be at logic 0 to enable the LVI module, and
the LVIRSTD bit must be at logic 1 to disable LVI resets.
The LVI interrupt flag, LVIIF, is set whenever the LVIOUT bit changes state (toggles). When LVIF is set,
a CPU interrupt request is generated if the LVIIE is also set. In the LVI interrupt service subroutine, LVIIF
bit can be cleared by writing a logic 1 to the LVI interrupt acknowledge bit, LVIIACK.
13.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register 1
(CONFIG1), the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable
LVI resets.
If LVIIE is set to enable LVI interrupts when LVIRSTD is cleared, LVI reset has a higher priority over LVI
interrupt. In this case, when VDD falls below the VTRIPF level, an LVI reset will occur, and the LVIIE bit will
be cleared.
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