參數(shù)資料
型號: MC68HC08LT8CFGE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù): 154/156頁
文件大?。?/td> 1107K
代理商: MC68HC08LT8CFGE
Port A
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
97
9.2.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to
a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1. Figure 9-4 shows the port
A I/O logic.
Figure 9-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 9-2 summarizes the operation of the port A pins.
Address:
$0004
Bit 7
6
54
32
1
Bit 0
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
000
00
000
Figure 9-3. Data Direction Register A (DDRA)
Table 9-2. Port A Pin Functions
DDRA
Bit
PTA Bit
I/O Pin Mode
Accesses to DDRA
Accesses to PTA
Read/Write
Read
Write
0
X(1)
1. X = don’t care.
Input, Hi-Z(2)
2. Hi-Z = high impedance.
DDRA[7:0]
Pin
PTA[7:0](3)
3. Writing affects data register, but does not affect input.
1
X
Output
DDRA[7:0]
PTA[7:0]
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INTE
RNAL
D
AT
A
B
U
S
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