參數(shù)資料
型號： MC68HC08LT8CFGE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.40 MM THICKNESS, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BCB, LQFP-44
文件頁數(shù)： 55/156頁
文件大小： 1107K
代理商： MC68HC08LT8CFGE
Electrical Specifications
MC68HC08LT8 Data Sheet, Rev. 1
148
Freescale Semiconductor
16.8 5-V Control Timing
16.9 3-V Control Timing
16.10 2-V Control Timing
Table 16-7. Control Timing (5V)
Characteristic(1)
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
Symbol
Min
Max
Unit
Internal operating frequency
fOP
—4
MHz
RST input pulse width low(2)
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
tIRL
100
—
ns
IRQ interrupt pulse width low (edge-triggered)(3)
3. Values are based on characterization results, not tested in production.
tILIH
100
—
ns
IRQ interrupt pulse period(3)
tILIL
Note(4)
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
—tCYC
Table 16-8. Control Timing (3V)
Characteristic(1)
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
Symbol
Min
Max
Unit
Internal operating frequency
fOP
—2
MHz
RST input pulse width low(2)
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
tIRL
250
—
ns
IRQ interrupt pulse width low (edge-triggered)(3)
3. Values are based on characterization results, not tested in production.
tILIH
250
—
ns
IRQ interrupt pulse period(3)
tILIL
Note(4)
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
—tCYC
Table 16-9. Control Timing (2V)
Characteristic(1)
1. VDD = 1.8 to 2.2 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
Symbol
Min
Max
Unit
Internal operating frequency
fOP
—1
MHz
RST input pulse width low(2)
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
tIRL
500
—
ns
IRQ interrupt pulse width low (edge-triggered)(3)
3. Values are based on characterization results, not tested in production.
tILIH
500
—
ns
IRQ interrupt pulse period(3)
tILIL
Note(4)
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
—tCYC
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