M44C510
TELEFUNKEN Semiconductors
Rev. A2, 13-Jan-98
14 (57)
Aux. Reg.
Subport 0
Subport 1
Subport Fh
Subport Eh
I/O bus
Aux. Reg.
Primary Reg.
Bank of
Primary Regs.
Primary Reg.
(Address Pointer)
Auxiliary Switch
Module
Indirect Subport
Access
Dual Register
Access
Single Register
Access
to other modules
Module M1
Module ASW
Module M2
Module M3
Address(M2) Address(ASW) OUT
Aux._Data
Address(M2) OUT
Prim._Data
Address(M2) OUT
(Primary Register Write)
Prim._Data Address(M3) OUT
(Primary Register Write)
Addr.(M1)
Addr.(ASW) OUT
Addr.(SPort) Addr.(M1)
OUT
1
2
(Subport Register Write)
SPort_Data
Addr.(M1)
OUT
3
4
5
6
1
2
3
4
7
5
6
Example of
qFORTH
Progra m
Code
Addr.(Mx) = Module Mx Addr ess
Aux._Data = data to be written into Auxilia ry Register
Prim._Data = data to be written into P rimary Register.
Addr.(M1)
Addr.(ASW) OUT
Addr.(SPort) Addr.(M1)
OUT
1
2
(Subport Register Read)
Addr.(M 1)
IN
Address(M2) Address(ASW) OUT
Address(M 2)
IN
(Auxiliary Register Rea d)
5
6
Address(M 2)
IN
(Primary Register Read)
4
Address(M1) Address(ASW) OUT
Address(M1) IN
(Auxiliary Register Rea d)
1
2
Address(M3) IN
(Prima ry Register Read)
7
Addr.(ASW) = Auxiliary Switch Module Address
Addr.(M1)
Addr.(ASW) OUT
Addr.(SPort) Addr.(M1)
OUT
1
2
(Subport Register Write Byte)
SPort_Data(lo) Addr.(M1) OUT
3
Addr.(M1)
Addr.(ASW) OUT
Addr.(SPort) Addr.(M1)
OUT
1
2
(Subport Register Rea d Byte)
Addr.(M 1)
IN
3
SPort_Data(hi) Addr.(M1) OUT
3
Addr.(M 1)
IN
3
SPort_Data(lo) = data to be written into SubP ort (low nibble)
SPort_Data(hi) = data to be written into Subport (high nibble)
Addr.(SPort) = Subport Address
Address(M2) Address(ASW) OUT
Aux._Data(lo) Address(M2) OUT
(Auxiliary Register Write Byte)
5
6
Aux._Data(hi) Address(M2) OUT
6
Aux._Data (lo)= data to be written into Auxiliary Register (low nibble)
Aux._Data (hi) = da ta to be written into Auxiliary Register(high nibble)
3
( Auxiliary Register Write )
96 11522
Figure 12. Example of I/O addressing