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參數(shù)資料
| 型號： | M44C510-P40 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 24/57頁 |
| 文件大?。?/td> | 1105K |
| 代理商： | M44C510-P40 |
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M44C510
TELEFUNKEN Semiconductors
Rev. A2, 13-Jan-98
30 (57)
2.5.2
Timer/Counter in 16-bit Mode
Prescaler
Counter
Prescaler
Carry
Comparator
Compare
Register
Compare
Register
Comparator
Overflow/compare
Compare
Interrupt
to TIM1
8bit/16bit
MUX
96 11549
Figure 24. 16-bit mode
In 16-bit mode, Timer 0 and Timer 1 are cascaded thus
forming a 16-bit counter (see figure 24) whereby, irre-
spective of the state of Timer 0 interrupt mask bit (T0IM),
the Timer 1 counts both Timer 0 overflow and compares
interrupt events. These are generated according to the
state of the Timer 0 Mode Register as described in the
T0MO table. The comparators are also cascaded so that
when both Timer 0 and Timer 1 match their respective
compare registers, the Timer 1 generates both an output
signal and a compare interrupt (if unmasked).
In measurement modes, only Timer 0 capture register is
loaded with Timer 0’s contents on an end-of-measure-
ment event. Timer 1 capture register operates solely as a
shadow register. There is no 16-bit capture operation, so
the user program must check if Timer 1 has incremented
between reading the lower and higher byte. Likewise,
there is no automatic suppression of spurious interrupts
which could conceivably be generated between writing
Timer 0 and Timer 1 compare registers.
2.5.3
Timer 0 Modes
The Timer 0 mode configuration is defined in the Timer 0
Mode Register (T0MO). The available modes and the
effect on the Timer 0 interrupt and interrupt flags is shown
below. In all modes except the position measurement
mode, Timer 0 acts as an up-counter, the related clock fre-
quency being defined by the selected clock source and the
prescaler division factor. The counter can be reset and
halted at any time by the T0RST bit of the TCMO register
which also resets all the interrupt status flags and capture
registers. Whenever Port 4 BP40 and BP41 pins are re-
quired for Timer 0 I/O, then the appropriate TCIOR
enable bit must be set low. In this case, the port direction
switching is handled automatically by the hardware. In
modes where the BP40 is not used as a timer clock input
or as a melody envelope output, the BP40 outputs the
same signal as that appearing on BP41. With the help of
the T0NINV bit of the Timer/Counter Mode Register
(TCMO), the BP41 output can be inverted so that BP40
and BP41 form a differential output stage which can be
used for directly driving piezo buzzers or small stepper
motors.
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