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參數(shù)資料
| 型號： | M44C510-P40 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 5/57頁 |
| 文件大?。?/td> | 1105K |
| 代理商： | M44C510-P40 |
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M44C510
TELEFUNKEN Semiconductors
Rev. A2, 13–Jan–98
13 (57)
1.5.1
Clock Monitor Mode
96 11521
SYSCL clocks
NRST
TE
BP10
Oscillator test mode
Normal operation
BP11
SUBCL clocks
Figure 11. Clock monitoring
For trimming purposes, the M44C510 can be put into a
clock monitor mode. The test input (TE) must therefore
be pulsed high once, whereupon the SYSCL clock will
appear on BP10 (Port 1, bit 0) and SUBCL clock on Port
BP11 (Port 1, bit 1). To put BP10 and BP11 back into
normal operation, the reset must be reapplied (see fig-
ure 11).
1.6
Sleep Mode
The sleep mode is a shutdown condition which is used to
reduce the average system power consumption in applica-
tions where the
C is not fully utilized. In this mode, the
system clock is stopped. The sleep mode is entered with
the SLEEP instruction. This instruction sets the condition
code register interrupt enable bit (I) to enable all inter-
rupts and stops the core. During the sleep mode, the
peripheral modules remain active and are able to generate
interrupts. The
C exits the sleep mode with any interrupt
or a reset. The sleep mode can only be maintained when
no interrupt pending or active register bits are set. The
application of the $AUTOSLEEP routine ensures the
correct function of the sleep mode. The total power con-
sumption is directly proportional to the active time of the
C. For a rough estimation of the expected average sys-
tem current consumption, the following formula should
be used:
Itotal (VDD,fsyscl) = ISleep + (IDD * Tactive /Ttotal)
IDD depends on VDD and fsyscl. Using a 32-kHz crystal,
the SLEEP current (ISleep) is typically less than 1 A. The
active time of the core and the total emulation time are
displayed in a separate window of the MARC4 emulator
software.
2
Peripheral Modules
2.1
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O
bus (see figure 12). The IN or OUT instructions allow
direct addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted which addresses the
“primary register” directly. To address the “auxiliary reg-
ister”, the access must be switched with an “auxiliary
switching module”. Thus, a single IN (or OUT) to the
module address will read (or write) into the module pri-
mary register. Accessing the auxiliary register is
performed with the same instruction preceded by writing
the module address into the auxiliary switching module.
Byte-wide registers are accessed by multiple IN (or OUT)
instructions. Extended addressing is used for more com-
plex peripheral modules, with a larger number of
registers. In this case, a bank of up to 16 subport registers
are indirectly addressed with the subport address being
initially written into the auxiliary register.
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