參數(shù)資料
型號： M44C510-P40
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁數(shù)： 27/57頁
文件大?。?/td> 1105K
代理商： M44C510-P40
M44C510
TELEFUNKEN Semiconductors
Rev. A2, 13–Jan–98
33 (57)
Timer 0 Compare Register (T0CP) – Byte Write
Subport address (indirect write access): ’9’hex
Bit 3
Bit 2
Bit 1
Bit 0
T0CP
First write cycle
T0CP3
T0CP2
T0CP1
T0CP0
Reset value: xxxxb
Bit 7
Bit 6
Bit 5
Bit 4
Second write cycle
T0CP7
T0CP6
T0CP5
T0CP4
Reset value: xxxxb
T0CP3 ... T0CP0 – Timer 0 Compare Register Data (low nibble) – first write cycle
T0CP7 ... T0CP4 – Timer 0 Compare Register Data (high nibble) – second write cycle
The compare register T0CP is 8-bit wide and must be accessed as byte wide subport (see section ”Addressing Peripher-
als). First of all, the data is written low nibble and is then followed by the high nibble. Any timer interrupts are
automatically suppressed until the complete compare value has been transferred.
Timer 0 Capture Register (T0CA) – Byte Read
Subport address (indirect read access): ’9’hex
Bit 7
Bit 6
Bit 5
Bit 4
T0CA
First read cycle
T0CA7
T0CA6
T0CA5
T0CA4
Reset value: 0000b
Bit 3
Bit 2
Bit 1
Bit 0
Second read cycle
T0CA3
T0CA2
T0CA1
T0CA0
Reset value: 0000b
T0CA7. .. T0CA4 – Timer 0 Capture Register Data (high nibble) – first read cycle
T0CA3 ... T0CA0 – Timer 0 Capture Register Data (low nibble) – second read cycle
Note:
If the timer is read (in PDM mode only) the bit order will appear reversed, so that T0CA0 =MSB,
T0CA1=MSB-1 .... T0CA6=LSB+1, T0CA7 = LSB.
The 8-bit capture register T0CA is read as byte wide subport. Note, however, unlike the writing to the compare register,
the high nibble is read first followed by the low nibble. The 8-bit timer state is captured on reading the first nibble and
held until the complete byte has been read. During this transfer, the timer is free to continue counting.
Note: Halting the timer after a capture/compare interrupt event will reset the capture register.
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