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參數(shù)資料
| 型號： | M44C510-P40 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 10/57頁 |
| 文件大?。?/td> | 1105K |
| 代理商： | M44C510-P40 |
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M44C510
TELEFUNKEN Semiconductors
Rev. A2, 13-Jan-98
18 (57)
2.2.2
Port 5, Port 7, Port C – Bidirectional Ports Type 2
These, and all other bidirectional ports include a bitwise-
programmable Data Direction Register (PxDDR) which
allows the individual programming of each port bit as
input or output. It also enables the reading of the pin
condition in output mode. This is a useful feature for self
testing and for serial bus applications.
Both type 2 and type 3 bidirectional ports have the same
I/O logic. Type 2, however, has an increased drive capa-
bility and type 3, an additional low resistance pull-up as
customer mask option.
Master reset
Q
BPxy
Mask options
*
PxDATy
PxDDRy
I/O Bus
D
I/O Bus
*
Pull-up
Pull-down
V
DD
*
Static
Pull-up
(Ports A, B)
(Data out)
(Direction)
*
S
D
*
S
96 11524
Figure 14. Bidirectional Ports 5, 7, A, B and C
2.2.3
Port A, Port B – Bidirectional Ports Type 3 – and Port Monitor Function
PxICR
BPx3
BPx2
BPx1
BPx0
Decoder
Connected to Ports A and B (x = A or B)
INT5
INT7
INT3
INT1
INT5
INT7
INT3
INT1
PxIPR
ENx3
ENx2
ENx1
ENx0
IMAx
ITRx
PRx1
PRx2
00
01
10
11
PRx1 PRx2
96 11529
Figure 15. Port monitor module
In addition to the standard I/O functions described in sec-
tion 2.2.2, both Port A (BPA3 – BPA0) and Port B (BPB3
– BPB0) are equipped with port monitor modules. This
module is connected across all four port pins (see fig-
ure 19)
and
generates
an
interrupt
should
a
pre-programmed transition occur on any of the selected
pins. This allows interrupt driven port scanning without
the power consuming task of continuously polling the
port inputs.
Using the Port Interrupt Control Register (PxICR), pins
can be individually selected. A non-selected pin cannot
generate an interrupt. The Port Interrupt Priority Register
(PxIPR) allows masking of each interrupt, definition of
the interrupt edge and programming of the interrupt
priority levels. Port A can also be used for a mask pro-
grammable coded reset. For more information see section
1.4 Hardware Reset.
The Port Interrupt Priority Registers PAIPR and PBIPR
are I/O mapped to the the primary address registers of the
Port Monitor Module addresses ’2’h and ’3’h respec-
tively. The Port Interrupt Control Registers PAICR and
PBICR are mapped to the corresponding auxiliary
registers.
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