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參數資料
| 型號： | M44C510-P40 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數： | 36/57頁 |
| 文件大?。?/td> | 1105K |
| 代理商： | M44C510-P40 |
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M44C510
TELEFUNKEN Semiconductors
Rev. A2, 13–Jan–98
41 (57)
Table 20.Timer 1 Control Register (T1CR)
Code
3 2 1 0
Function
x x x 1
Timer 1 interrupt disabled
x x x 0
Timer 1 interrupt enabled
0 0 0 x
Timer 1 prescaler divide by 256
0 0 1 x
Timer 1 prescaler divide by 128
0 1 0 x
Timer 1 prescaler divide by 64
0 1 1 x
Timer 1 prescaler divide by 32
1 0 0 x
Timer 1 prescaler divide by 16
1 0 1 x
Timer 1 prescaler divide by 8
1 1 0 x
Timer 1 prescaler divide by 4
1 1 1 x
Timer 1 prescaler bypassed
Timer 1 Compare Register (T1CP) – Byte Write
Subport address (indirect write access): ’8’hex
Bit 3
Bit 2
Bit 1
Bit 0
T1CP
First write cycle
T1CP3
T1CP2
T1CP1
T1CP0
Reset value: xxxxb
Bit 7
Bit 6
Bit 5
Bit 4
Second write cycle
T1CP7
T1CP6
T1CP5
T1CP4
Reset value: xxxxb
T1CP3 ... T1CP0 – Timer 1 Compare Register Data (low nibble) – first write cycle
T1CP7. .. T1CP4 – Timer 1 Compare Register Data (high nibble) – second write cycle
The compare register T1CP is 8 bits wide and must be accessed as byte wide subport (see section “Addressing Peripher-
als”). The data is written low nibble first, followed by high nibble. Any timer interrupts are automatically suppressed
until the complete compare value has been transferred.
Timer 1 Capture Register (T1CA) – Byte Read
Subport address (indirect read access): ’8’hex
Bit 7
Bit 6
Bit 5
Bit 4
T1CA
First read cycle
T1CA7
T1CA6
T1CA5
T1CA4
Reset value: 0000b
Bit 3
Bit 2
Bit 1
Bit 0
Second read cycle
T1CA3
T1CA2
T1CA1
T1CA0
Reset value: 0000b
T1CA7 ... T1CA4 – Timer 1 Capture Register Data (high nibble) – first read cycle
T1CA3 ... T1CA0 – Timer 1 Capture Register Data (low nibble) – second read cycle
The 8-bit capture register T1CA is read as byte-wide subport. Note, however, unlike the writing to the compare register,
the high nibble is read first followed by low nibble. The 8-bit timer state is captured on reading the first nibble and held
until the complete byte has been read. During this transfer, the timer is free to continue counting.
Note: Halting the timer after a capture/compare interrupt event will reset the capture register.
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