參數(shù)資料
型號(hào)： M44C510-P40
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁數(shù)： 54/57頁
文件大小： 1105K
代理商： M44C510-P40
M44C510
TELEFUNKEN Semiconductors
Rev. A2, 13-Jan-98
6 (57)
RAM
FCh
00h
Autosleep
FFh
03h
04h
X
Y
SP
RP
TOS–1
Expression
stack
Return
stack
Global
variables
RAM
address
register:
07h
(256 x 4-bit)
Global
variables
4-bit
TOS
TOS–1
TOS–2
30
SP
Expression stack
Return stack
0
11
12-bit
RP
v
94 8975
Figure 5. RAM map
ROM Banking Register (RBR)
The ROM banking register is a 4-bit register whereby in
the M44C510, only bit 2 is used. This indicates which
ROM bank is presently being addressed. The RBR is
accessed with a standard qFORTH peripheral read or
write instruction (IN or OUT, port address ‘D’ hex).
RAM Address Registers
The RAM is addressed with the four 8-bit wide RAM
address registers: SP, RP, X and Y. These registers allow
access to any of the 256 RAM nibbles.
Expression Stack Pointer (SP)
The stack pointer (SP) contains the address of the next-to-
top 4-bit item (TOS-1) of the expression stack. The
pointer is automatically preincremented if a nibble is
moved onto the stack, or postdecremented if a nibble is
removed from the stack. Every postdecrement operation
moves the item (TOS-1) to the TOS register before the SP
is decremented. After a reset the stack pointer has to be
initialized with “ >SP S0 ” to allocate the start address of
the expression stack area.
Return Stack Pointer (RP)
The return stack pointer points to the top element of the
12-bit wide return stack. The pointer automatically pre-
increments if an element is moved onto the stack or it
postdecrements if an element is removed from the stack.
The return stack pointer increments and decrements in
steps of 4. This means that every time a 12-bit element is
stacked, a 4-bit RAM location is left unwritten. These
locations are used by the qFORTH compiler to allocate
4-bit variables. After a reset, the return stack pointer has
to be initialized with “>RP FCh ”.
RAM Address Register ( X and Y )
The X and Y registers are used to address any 4-bit item
in the RAM. A fetch operation moves the addressed
nibble onto the TOS. A store operation moves the TOS to
the addressed RAM location. By using either the
preincrement or postdecrement, addressing mode arrays
in the RAM can be compared, filled or moved.
Top Of Stack ( TOS )
The top of stack register is the accumulator of the
MARC4. All arithmetic/logic, memory reference and I/O
operations use this register. The TOS register receives
data from the ALU, ROM, RAM or I/O bus.
Condition Code Register ( CCR )
The 4-bit wide condition code register contains the
branch, the carry and the interrupt-enable flag. These bits
indicate the current state of the CPU. The CCR flags are
set or reset by ALU operations. The instructions
SET_BCF, TOG_BF, CCR! and DI allow direct
manipulation of the condition code register.
Carry/Borrow ( C )
The carry/borrow flag indicates that borrow or carry out
of arithmetic logic unit ( ALU ) occurred during the last
arithmetic operation. During shift and rotate operations,
this bit is used as a fifth bit. Boolean operations have no
affect on the C flag.
Branch ( B )
The branch flag controls the conditional program branch-
ing. Should the branch flag have been set by a previous
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