
deveopmen
Interrupts
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
98
External interrupt request cause select register
AAA
Bit name
Function
Bit symbol
Symbol
IFSR
Address
031F
16
When reset
00
16
IFSR0
b3
b2
b1
b0
INT0 interrupt polarity
select bit (Note)
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
INT1 interrupt polarity
select bit (Note)
INT2 interrupt polarity
select bit (Note)
INT3 interrupt polarity
select bit (Note)
INT4 interrupt polarity
select bit (Note)
INT5 interrupt polarity
select bit (Note)
0 : One edge
1 : Both edges
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
AA
AA
AA
AA
AA
AA
AA
AA
Note :When level sense is selected, set this bit to "0".
When both edges are selected, set the corresponding polarity switching bit of INT interrupt control
register to "0" (falling edge).
0 : UART3 bus collision /start,stop
detect/false error detect
1 : UART0 bus collision /start,stop
detect/false error detect
UART0/3 interrupt
cause select bit
UART1/4 interrupt
cause select bit
IFSR6
IFSR7
AA
AA
AA
0 : UART4 bus collision /start,stop
detect/false error detect
1 : UART1 bus collision /start,stop
detect/false error detect
______
INT0 to INT5 are external input interrupts. The level sense/edge sense switching bits of the interrupt control
register select the input signal level and edge at which the interrupt can be set to occur on input signal level
and input signal edge. The polarity bit selects the polarity.
With the external interrupt input edge sense, the interrupt can be set to occur on both rising and falling
edges by setting the INTi interrupt polarity switch bit of the interrupt request select register (address
031F
16
) to
“
1
”
. When you select both edges, set the polarity switch bit of the corresponding interrupt control
register to the falling edge (
“
0
”
).
When you select level sense, set the INTi interrupt polarity switch bit of the interrupt request select register
(address 031F
16
) to
“
0
”
.
Figure 1.9.10 shows the interrupt request select register.
Figure 1.9.10. External interrupt request cause select register