deveopmen
Intelligent I/O (Serial I/O)
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
278
Figure 1. 23. 37. Group 2 Intelligent I/O-related register (4)
b7
b0
GMD0
GMD1
CKDIR
Communication mode
select bit
UFORM
IRS
Internal/external clock
select bit
Transfer direction
select bit
Transmit interrupt
cause select bit
0 : Internal clock
1 : External clock
0 : LSB first
1 : MSB first
0 : Transmit buffer is empty
1 : Transmit is completed
: Communication part is reset
(Overrun error flag is cleared)
: Serial I/O mode
: Special communication mode
: HDLC data process mode
b1
0
0
1
1
b0
0
1
0
1
(Note 2)
(Note 3)
Group 2 SI/O communication mode register
Symbol
G2MR
Address
016A
16
When reset
00XXX000
2
R W
Bit name
Function
Bit
symbol
Note 1: Intelligent I/O group 2 has IE bus communication function as special communication function.
Note 2: Select a pin for clock output by setting the waveform generation control register, input function select
register, and function select registers A, B and C. Data transmission pins are the same as clock
output pins.
Note 3: Select which pins will input the clock with the input function select register and set those pins to the
input port using function select register A. Data input pins are the same as with clock input pins.
Nothing is assigned. When write, set "0".
When read, their contents are indeterminate.
Group 2 SI/O communication control register
Symbol
G2CR
Address
016B
16
When reset
0000 X000
2
R W
Bit name
Function
Bit
symbol
Nothing is assigned. When write, set to "0".
When read, the contents is indeterminate.
b7
b0
TE
TXEPT
RI
Transmit enable bit
TI
RE
IPOL
OPOL
Receive complete
flag
Transmit buffer
empty flag
Receive enable bit
RxD input polarity
reverse select bit
TxD output polarity
reverse select bit
0 :
No data present in receive buffer register
1 : Data present in receive buffer register
0 :
Data present in transmit buffer register
1 :
No data present in transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No reverse (Usually set to "0")
1 : Reverse
Transmit register
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
0 : No reverse (Usually set to "0")
1 : Reverse