deveopmen
Rev.B2 for proof reading
Reset
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
31
(0198
16
)
(0199
16
)
(019A
16
)
(019B
16
)
(019C
16
)
(019D
16
)
(019E
16
)
(019F
16
)
(01A0
16
)
(01A1
16
)
(01A2
16
)
(01A3
16
)
(01A6
16
)
(01A7
16
)
(01AB
16
)
(01AC
16
)
(01AD
16
)
(01AE
16
)
(01AF
16
)
(01B0
16
)
(01B1
16
)
(01B2
16
)
(01B3
16
)
(01B4
16
)
(01B5
16
)
(01B6
16
)
(01B7
16
)
(01B8
16
)
(01B9
16
)
(01BA
16
)
(01BB
16
)
(01BC
16
)
(01BD
16
)
(0173
16
)
(0174
16
)
(0178
16
)
(017A
16
)
(017B
16
)
(017C
16
)
(017D
16
)
(017E
16
)
(017F
16
)
(0180
16
)
(0181
16
)
(0182
16
)
(0183
16
)
(0184
16
)
(0185
16
)
(0186
16
)
(0187
16
)
(0188
16
)
(0189
16
)
(018A
16
)
(018B
16
)
(018C
16
)
(018D
16
)
(018E
16
)
(018F
16
)
(0190
16
)
(0191
16
)
(0192
16
)
(0193
16
)
(0194
16
)
(0195
16
)
(0196
16
)
(0197
16
)
Input function select register
Group 3 SI/O communication mode register
Group 3 SI/O communication control register
Group 3 SI/O transmit buffer register
Group 3 SI/O receive buffer register
Group 3 waveform generate register 0
Group 3 waveform generate register 1
Group 3 waveform generate register 2
Group 3 waveform generate register 3
Group 3 waveform generate register 4
Group 3 waveform generate register 5
Group 3 waveform generate register 6
Group 3 waveform generate register 7
Group 3 waveform generate control register 0
Group 3 waveform generate control register 1
Group 3 waveform generate control register 2
Group 3 waveform generate control register 3
Group 3 waveform generate control register 4
Group 3 waveform generate control register 5
Group 3 waveform generate control register 6
Group 3 waveform generate control register 7
(215)
(216)
(217)
(218)
(219)
(220)
(221)
(222)
(223)
(224)
(225)
(226)
(227)
(228)
(229)
(230)
(231)
(232)
(233)
(234)
(235)
(236)
(237)
(238)
(239)
(240)
(241)
(242)
(243)
(244)
(245)
(246)
(247)
(248)
(249)
(250)
(251)
(252)
(253)
(254)
(255)
(256)
(257)
Group 3 waveform generate mask register 4
Group 3 waveform generate mask register 5
Group 3 waveform generate mask register 6
Group 3 waveform generate mask register
7
Group 3 base timer register
Group 3 base timer control register 0
Group 3 base timer control register 1
Group 3 function enable register
Group 3 RTP output
buffer
register
Group 3 high-speed HDLC
communication
control register 1
Group 3 high-speed HDLC
communication
control register
Group 3 high-speed HDLC
communication
register
Group 3 high-speed HDLC transmit counter
Group 3 high-speed HDLC data
compare register 0
Group 3 high-speed HDLC data
mask register 0
Group 3 high-speed HDLC data
compare register 1
Group 3 high-speed HDLC data
mask register 1
Group 3 high-speed HDLC data
compare register 2
Group 3 high-speed HDLC data
mask register 2
Group 3 high-speed HDLC data
compare register 3
XXX00 0 0 0
XXX00 0 0 0
00 0X 0
00XX000 0
0XX0X00 0
Group 2 IEBus transmit interrupt
cause detect register
Group 2 IEBus receive interrupt
cause detect register
00
16
00
16
00
16
00
16
00
16
00
16
16
16
00
16
00
16
00
16
00
16
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
16
16
16
16
00
16
x : Nothing is mapped to this bit
: Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
00XXXXX0
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Figure 1.4.3. Device's internal status after a reset is cleared (5/10)