deveopmen
UARTi Special Mode Register
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
189
The start condition detection interrupt is generated when the falling edge at the SDAi pin is detected
while the SCLi pin is in the H state. The stop condition detection interrupt is generated when the rising
edge at the SDAi pin is detected while the SCLi pin is in the H state.
The acknowledge non-detection interrupt is generated when the H level at the SDAi pin is detected at
the 9th rise of the transmission clock.
The acknowledge detection interrupt is generated when the L level at the SDAi pin is detected at the
9th rise of the transmission clock. Also, DMA transfer can be started when the acknowledge is de-
tected and UARTi transmission is selected as the DMAi request factor.
Bit 1 is the arbitration lost detection flag control bit (ABC). Arbitration detects a conflict between data
transmitted at SCLi rise and data at the SDAi pin. This detection flag is allocated to bit 11 in UARTi
transmission buffer register (addresses 036F
16
, 02EF
16
, 033F
16
, 032F
16
, 02FF
16
). It is set to
“
1
”
when
a conflict is detected. With the arbitration lost detection flag control bit, it can be selected to update the
flag in units of bits or bytes. When this bit is set to
“
1
”
, update is set to units of byte. If a conflict is then
detected, the arbitration lost detection flag control bit will be set to
“
1
”
at the 9th rise of the clock. When
updating in units of byte, always clear (
“
0
”
interrupt) the arbitration lost detection flag control bit after
the 1st byte has been acknowledged but before the next byte starts transmitting.
Bit 2 is the bus busy flag (BBS). It is set to
“
1
”
when the start condition is detected, and reset to
“
0
”
when the stop condition is detected.
Bit 3 is the SCLi L synchronization output enable bit (LSYN). When this bit is set to
“
1
”
, the port data
register is set to
“
0
”
in sync with the L level at the SCLi pin.
Bit 4 is the bus collision detection sampling clock select bit (ABSCS). The bus collision detection
interrupt is generated when RxDi and TxDi level do not conflict with one another. When this bit is
“
0
”
,
a conflict is detected in sync with the rise of the transfer clock. When this bit is
“
1
”
, detection is made
when timer Ai (timer A3 with UART0, timer A4 with UART1, timer A0 with UART2, timer A3 with
UART3 and timer A4 with UART4) underflows. Operation is shown in Figure 1.21.2.
Bit 5 is the transmission enable bit automatic clear select bit (ACSE). By setting this bit to
“
1
”
, the
transmission bit is automatically reset to
“
0
”
when the bus collision detection interrupt factor bit is
“
1
”
(when a conflict is detected).
Bit 6 is the transmission start condition select bit (SSS). By setting this bit to
“
1
”
, TxDi transmission
starts in sync with the rise at the RxDi pin.