
REVISION HISTORY
M32C/83 GROUP DATA SHEET
Rev.
Date
Description
Page
Errror
Correct
( 1 / 7 )
B1
1/8/2001
100-pin version is added.
Flash memory version is added.
Others
2,3
Tables 1.1.1 and 1.1.2
Interrupt: 12 internal/external sources
(intelligent I/O and CAN module)
Supply voltage
A-D converter
10 bits (8 channels) x 2 circuits, max 26 inputs
Table 1.1.3
Pin 26
10-12 Figures 1.1.4, 1.1.5, Table 1.1.7
11
Figure 1.1.5 Pin 97 AN0
0
12
Pin 32 (FP)
Vcc
Pin 34 (FP)
Vss
13
Vcc position to pin 64(FP)
Vss position to pin 66(FP)
RxD4/SCL4/STxD4 position to pin 98 (FP)
14
Table 1.1.5
AN2
0
to AN2
7
AN3
0
to AN3
7
17
Table1.1.12
P12
0
to P12
7
ISCLK description
AN1
0
to AN1
7
18
Figure 1.1.6 System clock oscillation circuit
28, 29 Figure 1.4.3 (122), (167)
Delate
3.0 to 3.6V (f(X
IN
)=20MHz without wait) add
3
10 bits x 2 circuits, standard 10 inputs, max 26 inputs
CAN
IN
addition
CAN
IN
is added to Pin 17(GP) and pin 19(FP)
AN
0
Delate
Delate
Pin 62
Pin 64
Pin 100
AN0
0
to AN0
7
AN2
0
to AN2
7
Delate
AN15
0
to AN15
7
PLL oscillation stop detect addition
Group0 receive buffer register, Group1 receive buffer
register
Group0 transmit buffer/receive data register, Group1
transmit buffer/receive data register
Addresses 03A0
16
, 03A1
16
, 03B9
16
, 03BC
16
, 03BD
16
,
03C9
16
, 03CB
16
to 03D3
16
Addition. Displase after the former Note 2
7
(123), (168)
46
Note 1: Addresses 03C9
16
, 03CB
16
to 03D3
16
48
70
Figure 1.6.1 Note 2
Figure 1.8.6
When reset of PLL control register 0
0X11 0100
Figure 1.8.8 Count value set bit
Count start bit
Count stop/start
Note 2
Line 10
Addition
Line 8
1:Sub clock is selected
Figure 1.14.2 Values that can be set Pulse width
modulation mode (8-bit PWM)
00
16
to FF
16
(High-order and low-order address)
0011 0100
Division rate select bit
Operation enable bit
Divider stops/starts
Delate
Stop mode is canceled before setting this bit to "1".
1: Clock from ring oscillator is selected
72
76
77
135
00
16
to FE
16
(High-order address) 00
16
to FF
16
(Low-
order address)
TrmData
230
266
Line 5, Bit 1
Table1.23.11 Waveform generate control register
1when clock synchronous serial I/O
-
Table1.23.17 Note 1:
TrmActive
√
When the transfer clock and transfer data are trans-
mission, transfer clock is set to at least 6 divisions of
280
B1
30/8/
2001