deveopmen
Interrupts
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
104
Bit 0: Interrupt request latch bit (IRLT)
An interrupt signal or latched signal of the interrupt signal is selected as an interrupt request signal.
When the latched signal of an interrupt signal is used, this flag must be set to "0" after interrupt request
flag is read in interrupt process routine, . If this flag is not set to "0" and interrupt process is completed,
although interrupt request occurs again, interrupt will not occur.
Bit 1 to bit 7: Interrupt enable bit (ITE 1 to ITE 7)
To enable/disable respective interrupts.
Precautions for Interrupts
(1) Reading addresses 000000
16
and 000002
16
When maskable interrupt occurs, CPU reads the interrupt information (the interrupt number and inter-
rupt request level) in the interrupt sequence from address 000000
16
. When a high-speed interrupt
occurs, CPU reads from address 000002
16
.
The interrupt request bit of the certain interrupt will then be set to
“
0
”
.
However, reading addresses 000000
16
and 000002
16
by software does not set request bit to
“
0
”
.
(2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 000000
16
. Accepting an interrupt
before setting a value in the stack pointer may cause runaway. Be sure to set a value in the stack
pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the
beginning of a program. Any interrupt including the NMI interrupt is generated immediately after ex-
ecuting the first instruction after reset. Set an even number to the stack pointer. Set an even address
to the stack pointer so that operating efficiency is increased.
(3) The NMI interrupt
As for the NMI interrupt pin, this interrupt cannot be disabled. Connect it to the Vcc pin via a pull-up
resistor if unused.
The NMI pin also serves as P8
5
, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
when the NMI interrupt is input.
A low level signal with more than 1 clock cycle (BCLK) is necessary for NMI pin.
(4) External interrupt
Edge sense
Either a low level or a high level for at least 250 ns is necessary for the signal input to pins INT
0
to INT
5
regardless of the CPU operation clock.
Level sense
Either a low level or a high level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT
0
to INT
5
regardless of the CPU operation clock. (When X
IN
=20MHz and no division
mode, at least 250 ns width is necessary.)