
deveopmen
Serial I/O
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
173
UARTi transmit/receive control register 1
(i=0 to 4)
Symbol
UiC1(i=0 to 4)
Address
036D
16,
02ED
16,
033D
16,
032D
16,
02FD
16
When reset
02
16
R W
RI
UiIRS
UiRRM
UiLCH
TE
RE
TI
Transmit
enable bit
Transmit buffer
empty flag
Receive
enable bit
Receive
complete flag
Clock divide
synchronizing stop bit
/e
rror signal output
enable bit
SCLKSTPB
/UiERE
UARTi transmit
interrupt cause
select bit
UARTi
continuous
receive mode
enable bit
Data logic
select bit
0: Transmission disabled
1: Transmission enabled
0: Data present in transmit buffer register
0: No data present in transmit buffer register
0: Reception disabled
1: Reception enabled
0: Data present in receive buffer register
0: No data present in receive buffer register
0: Transmit buffer empty (TI = 1)
1: Transmit is completed (TXEPT = 1)
0: Continuous receive
mode disabled
1: Continuous receive
mode enabled
Set to
“
0
”
0: No reverse
1: Reverse
Clock divide synchronizing stop bit
0:
Synchronizing
stop
1: Synchronous start
(Note)
Note :When this bit and bit 7 of UARTi special mode register 2 are set, clock synchronizing function is used.
Bit name
Bit
symbol
(serial I/O mode)
Function
(UART mode)
Set to
“
0
”
b7
b6
b5
b4
b3
b2
b1
b0
UARTi special mode register
(i=0 to 4)
Symbol
UiSMR(i=0 to 4)
Address
0367
16,
02E7
16,
0337
16,
0327
16,
02F7
16
00
16
When reset
R W
LSYN
ABSCS
ACSE
SSS
IICM
BBS
ABC
0: Normal mode
1: IIC mode
0: Update per bit
1: Update per byte
0: STOP condition
detected
1: START condition
detected
0: Disabled
1: Enabled
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
Set to "0"
0: Ordinary
1: Falling edge of RxDi
0: Rising edge of transfer clock
1: Underflow signal of timer Ai
(Note 2)
Bit name
Bit
symbol
(serial I/O mode)
Function
(UART mode)
IIC mode
select bit
Bus busy flag
Note 1: Nothing but "0" may be written.
Note 2: UART0: timer A3 underflow signal, UART1: timer A4 underflow signal, UART2: timer A0 underflow signal,
UART3: timer A3 underflow signal, UART4: timer A4 underflow signal.
Note 3: When this bit and bit 7 of UARTi transmit/receive control register 1 are set, clock synchronizing
function is used.
Auto clear function
select bit of transmit
enable bit
Transmit start
condition
select bit
SCLL sync
output enable
bit
Bus collision
detect sampling
clock select bit
Arbitration lost
detecting flag
control bit
0: No auto clear function
1: Auto clear at
occurrence of bus
(Note 1)
SCLKDIVClock divide
set bit
0: Divided-by-2
1: No divided
(Note 3)
b7
b6
b5
b4
b3
b2
b1
b0
Figure 1.17.5. Serial I/O-related registers (4)