deveopmen
Processor Mode
Rev.B2 for proof reading
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
21
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). Registers R2 and R0, as well as R3 and R1 can function as 32-bit data
registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 24 bits, and have functions equivalent to those of data
registers. These registers can also function as address register, indirect addressing and address register
relative addressing.
(3) Static base register (SB)
Static base register (SB) is configured with 24 bits, and is used for SB relative addressing.
(4) Frame base register (FB)
Frame base register (FB) is configured with 24 bits, and is used for FB relative addressing.
(5) Program counter (PC)
Program counter (PC) is configured with 24 bits, indicating the address of an instruction to be executed.
(6) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 24 bits, indicating the start address of an interrupt vector
table.
(7) User stack pointer (USP), interrupt stack pointer (ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 24 bits.
The desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This
flag is located at bit 7 in the flag register (FLG).
To execute efficienly set USP and ISP to an even number.
(8) Save flag register (SVF)
This register consists of 16 bits and is used to save the flag register when a high-speed interrupt is
generated.
(9) Save PC register (SVP)
This register consists of 24 bits and is used to save the program counter when a high-speed interrupt is
generated.
This register consist of 24 bits and is used to indicate a jump address when a high-speed interrupt is
generated.