deveopmen
Rev.B2 for proof reading
DMAC
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
112
Setting value
DMA request cause
b4 b3 b2 b1 b0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
DMA0
Falling edge of INT0 pin
Both edges of INT0
DMA1
DMA2
Falling edge of INT2 pin
Both edges of INT2
DMA3
Falling edge of INT3 pin
Both edges of INT3
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
UART0 transmit
UART0 receive /ACK
UART1 transmit
UART1 receive /ACK
UART2 transmit
UART2 receive /ACK
UART3 transmit
UART3 receive /ACK
UART4 transmit
UART4 receive /ACK
Falling edge of INT1 pin
Both edges of INT1
A-D0
Intelligent I/O interrupt
control register 0
Intelligent I/O interrupt
control register 1
Intelligent I/O interrupt
control register 2
Intelligent I/O interrupt
control register 3
Intelligent I/O interrupt
control register 4
Intelligent I/O interrupt
control register 5
Intelligent I/O
interrupt
control register 6
A-D1
Intelligent I/O interrupt
control register 7
Intelligent I/O interrupt
control register 8
Intelligent I/O interrupt
control register 9
Intelligent I/O interrupt
control register 10
Intelligent I/O interrupt
control register 11
Intelligent I/O interrupt
control register 0
Intelligent I/O interrupt
control register 1
A-D0
Intelligent I/O interrupt
control register 2
Intelligent I/O interrupt
control register 3
Intelligent I/O interrupt
control register 4
Intelligent I/O interrupt
control register 5
Intelligent I/O interrupt
control register 6
Intelligent I/O interrupt
control register 7
Intelligent I/O interrupt
control register 8
A-D1
Intelligent I/O interrupt
control register 9
Intelligent I/O interrupt
control register 10
Intelligent I/O interrupt
control register 11
Intelligent I/O interrupt
control register 0
Intelligent I/O interrupt
control register 1
Intelligent I/O interrupt
control register 2
Intelligent I/O interrupt
control register 3
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Note 1: When INT3 pin is data bus in microprocessor mode, INT3 edge cannot be used as DMA3 request cause.
Note 2: UARTi receive /ACK switched by setting of UARTi special mode register and UARTi special mode
register 2 (i=0 to 3)
(Note 1)
(Note 1)
Table 1.11.2. DMAi request cause select register function