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參數(shù)資料
| 型號： | LRS1338A |
| 廠商： | Sharp Corporation |
| 英文描述： | Stacked Chip 8M Flash Memory and 2M SRAM |
| 中文描述： | 堆疊芯片800萬快閃記憶體以及2M SRAM |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 218K |
| 代理商： | LRS1338A |
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LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
8
Data Sheet
Table 4. Flash Pin Descriptions
SYMBOL
TYPE
NAME AND FUNCTION
A
0
- A
18
Input
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during the write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; out-
puts data during memory array, status register, and identifier code read cycles. Data
pins float to HIGH-impedance when the chip is deselected or outputs are disabled.
Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device
’
s control logic, input buffers, decoders, and
sense amplifiers. CE-HIGH deselects the device and reduces power consumption
to standby levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and
resets internal automation. RP-HIGH enables normal operation. When driven
LOW, RP inhibits write operations which provides data protection during power
transitions. Exit from deep power-down sets the device to read array mode. With
RP = V
HH
, block erase or word write can operate to all blocks without WP state.
Block erase or word write with V
IH
< RP < V
HH
produce spurious results and should
not be attempted.
OUTPUT ENABLE: Gates the device
’
s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CIU and array blocks. Addresses and data
are latched on the rising edge of the WE pulse.
WRITE PROTECT: Master control for boot blocks locking. When V
IL
, locked boot
blocks cannot be erased and programmed.
BLOCK ERASE and WORD WRITE POWER SUPPLY: For erasing array blocks or
writing words. With V
PP
≤
V
PPLK
, memory contents cannot be altered. Block erase
and word write with an invalid V
PP
(see
‘
DC Characteristics
’
) produce spurious
results and should not be attempted.
DEVICE POWER SUPPLY: Do not float any power pins. With V
CC
≤
V
LKO
, all
write attempts to the flash memory are inhibited. Device operations at invalid
V
CC
voltage (see
‘
DC Characteristics
’
) produce spurious results and should not
be attempted.
GROUND: Do not float any ground pins.
I/O
0
- I/O
15
Input/Output
CE
Input
RP
Input
OE
Input
WE
Input
WP
Input
V
PP
Supply
V
CC
Supply
GND
Supply
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LRS1341 | Stacked Chip 16M Flash Memory and 2M SRAM |
| LRS1805A | Stacked Chip 64M (x16) Flash Memory + 16M (x16) Smartcombo RAM |
| LRS250 | LIGHT EMITTING DIODES |
| LRS250-DO | LIGHT EMITTING DIODES |
| LRZ180-CO | Array LED 2 mm LED, Diffused |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LRS1341 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Stacked Chip 16M Flash Memory and 2M SRAM |
| LRS1342 | 制造商:Sharp Microelectronics Corporation 功能描述:COMBO 1MX16 FLASH + 128KX16 SRAM 2.7V TO 3.6V 72FBGA - Trays |
| LRS1348 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LRS1360 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LRS1360C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|72PIN|PLASTIC |
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