參數(shù)資料
型號： LRS1338A
廠商： Sharp Corporation
英文描述： Stacked Chip 8M Flash Memory and 2M SRAM
中文描述： 堆疊芯片800萬快閃記憶體以及2M SRAM
文件頁數(shù)： 19/36頁
文件大小： 218K
代理商： LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
Data Sheet
19
Design Considerations
THREE-LINE OUTPUT CONTROL
The device will often be used in large memory
arrays. SHARP provides three control inputs to accom-
modate multiple memory connections. Three-line con-
trol provides for:
Lowest possible memory power dissipation.
Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE while OE should be con-
nected to all memory devices and the system
’
s READ
control line. This assures that only selected memory
devices have active outputs while deselected memory
devices are in standby mode. RP should be connected
to the system POWERGOOD signal to prevent unin-
tended writes during system power transitions. POW-
ERGOOD should also toggle during system reset.
POWER SUPPLY DECOUPLING
Flash memory power switching characteristics
require careful device decoupling. System designers
are interested in three supply current issues: standby
current levels, active current levels and transient peaks
produced by falling and rising edges of CE and OE.
Transient current magnitudes depend on the device
outputs
’
capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device should
have a 0.1 μF ceramic capacitor connected between its
V
CC
and GND and between its V
PP
and GND. These
high-frequency, low inductance capacitors should be
placed as close as possible to package leads. Addition-
ally, for every eight devices, a 4.7 μF electrolytic capac-
itor should be placed at the array
’
s power supply
connection between V
CC
and GND. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductance.
V
PP
TRACE ON PRINTED CIRCUIT BOARDS
Updating flash memories that reside in the target
system requires that the printed circuit board designer
pay attention to the V
PP
power supply trace. The V
PP
pin supplies the memory cell current for word writing
and block erasing. Use similar trace widths and layout
considerations given to the V
CC
power bus. Adequate
V
PP
supply traces and decoupling will decrease V
PP
voltage spikes and overshoots.
V
CC
, V
PP
RP TRANSITIONS
Block erase and word write are not guaranteed if
V
PP
falls outside of a valid V
PPH
range, V
CC
falls out-
side of a valid V
CC1
range, or RP
≠
V
IH
or V
HH
. If V
PP
error is detected, status register bit SR.3 is set to
‘
1
’
along with SR.4 or SR.5, depending on the attempted
operation. If RP transitions to V
IL
during block erase or
word write, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP transitions to V
IL
clear
the status register.
The CIU latches commands issued by system soft-
ware and is not altered by V
PP
or CE transitions or
WSM actions. Its state is read array mode upon power-
up, after exit from deep power-down or after V
CC
tran-
sitions below V
LKO
.
After block erase or word write, even after V
PP
tar-
nation down to V
PPLK
, the CUI must be placed in read
array mode via the Read Array command if subsequent
access to the memory array is desired.
POWER-UP/DOWN PROTECTION
The device is designed to offer protection against
accidental block erasure or word writing during power
transitions. Upon power-up, the device is indifferent as
to which power supply (V
PP
or V
CC
) powers-up first.
Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is active.
Since both WE and CE must be LOW for a command
write, driving either to V
HH
will inhibit writes. The CUI
’
s
two-step command sequence architecture provides
added level of protection against data alteration.
WP provide additional protection from inadvertent
code or data alteration.
The device is disabled while RP = V
IL
regardless of
its control inputs state.
POWER DISSIPATION
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during sys-
tem idle time. Flash memory
’
s non-volatility increases
usable battery life because data is retained when sys-
tem power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can con-
sume negligible power by lowering RP to V
IL
standby or
sleep modes. If access is again needed, the devices
can be read following the t
PHQV
and t
PHWL
wake-up
cycles required after RP is first raised to V
IH
. See
‘
AC
Characteristics
—
Read Only and Write Operations
’
and Figure 12, 13 and 14 for more information.
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相關代理商/技術參數(shù)
參數(shù)描述
LRS1341 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Stacked Chip 16M Flash Memory and 2M SRAM
LRS1342 制造商:Sharp Microelectronics Corporation 功能描述:COMBO 1MX16 FLASH + 128KX16 SRAM 2.7V TO 3.6V 72FBGA - Trays
LRS1348 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM
LRS1360 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM
LRS1360C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|72PIN|PLASTIC
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