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參數(shù)資料
| 型號： | LRS1338A |
| 廠商： | Sharp Corporation |
| 英文描述： | Stacked Chip 8M Flash Memory and 2M SRAM |
| 中文描述： | 堆疊芯片800萬快閃記憶體以及2M SRAM |
| 文件頁數(shù)： | 34/36頁 |
| 文件大?。?/td> | 218K |
| 代理商： | LRS1338A |
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LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
34
Data Sheet
Figure 19. Write Cycle Timing Diagram (OE LOW Fixed)
Figure 20. Data Retention Timing Diagram
t
DW
t
DH
t
WP
t
WC
t
AW
t
CW
t
WR
t
OW
t
WZ
t
AS
DATA VALID
(NOTE 3)
(NOTE 1)
t
WR
(NOTE 3)
(NOTE 4)
(NOTE 6)
(NOTE 2)
ADDRESS
CE
WE
D
OUT
D
IN
(NOTE 5)
1338A-19
NOTES:
1.
t
CW
is measured from the later of CE going LOW to the end of write.
2.
t
AS
is measured from the address valid to the beginning of write.
3.
t
WR
is measured from the end of write to the address change. t
WR
applies
in case a write ends at CE or WE going HIGH.
4.
During this period, I/O pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
5.
If CE goes LOW simultaneously with WE going LOW or after WE going LOW,
the outputs remain in HIGH impedance state.
6.
If CE goes HIGH simultaneously with WE going HIGH or before WE going HIGH,
the outputs remain in HIGH impedance state.
Data Retention Mode
2.7 V
0 V
2.0 V
V
CCDR
V
CC
CE
CE
≥
V
CCDR
- 0.2 V
t
CDR
t
R
1338A-20
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LRS1341 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Stacked Chip 16M Flash Memory and 2M SRAM |
| LRS1342 | 制造商:Sharp Microelectronics Corporation 功能描述:COMBO 1MX16 FLASH + 128KX16 SRAM 2.7V TO 3.6V 72FBGA - Trays |
| LRS1348 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LRS1360 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LRS1360C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|72PIN|PLASTIC |
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