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參數(shù)資料
| 型號(hào)： | LRS1338A |
| 廠商： | Sharp Corporation |
| 英文描述： | Stacked Chip 8M Flash Memory and 2M SRAM |
| 中文描述： | 堆疊芯片800萬快閃記憶體以及2M SRAM |
| 文件頁數(shù)： | 33/36頁 |
| 文件大小： | 218K |
| 代理商： | LRS1338A |
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Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
Data Sheet
33
Figure 18. Write Cycle Timing Diagram (OE Controlled)
t
WC
t
AW
t
WR
t
WR
t
AS
t
OHZ
t
DW
t
DH
t
CWP
t
WP
ADDRESS
OE
CE
WE
D
OUT
D
IN
Data Valid
1338A-18
(NOTE 4)
(NOTE 2)
(NOTE 3)
(NOTE 6)
(NOTE 5)
(NOTE 1)
(NOTE 4)
NOTES:
1. A write occurs during the overlap of a LOW CE and a LOW WE.
A write begins at the latest transition among CE going LOW and WE going LOW.
A write ends at the earliest transition among CE going HIGH and WE going HIGH.
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the later of CE going LOW to the end of write.
3.
t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change. t
WR
applies
in case a write ends at CE or WE going HIGH.
5.
During this period, I/O pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
6.
If CE goes LOW simultaneously with WE going LOW or after WE going LOW,
the outputs remain in HIGH impedance state.
7.
If CE goes HIGH simultaneously with WE going HIGH or before WE going HIGH,
the outputs remain in HIGH impedance state.
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相關(guān)代理商/技術(shù)參數(shù) |
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