參數(shù)資料
型號(hào)： LRS1338A
廠商： Sharp Corporation
英文描述： Stacked Chip 8M Flash Memory and 2M SRAM
中文描述： 堆疊芯片800萬(wàn)快閃記憶體以及2M SRAM
文件頁(yè)數(shù)： 20/36頁(yè)
文件大小： 218K
代理商： LRS1338A
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
20
Data Sheet
Electrical Specifications
ABSOLUTE MAXIMUM RATINGS
*
Commercial Operating Temperature
–
During Read, Block Erase and Word Write:
-40
°
C to +85
°
C (Note 1)
–
Temperature under Bias: -40
°
C to +85
°
C (Note 1)
Storage Temperature: -65
°
C to +125
°
C
Voltage on any pin except V
CC
, V
PP
and RP:
-2.0 V to +7.0 V (Note 2)
V
CC
Supply Voltage: -2.0 V to +7.0 V (Note 2)
V
PP
Update Voltage during Block Erase and Word
Write: -2.0 V to +14.0 V (Note 2 and 3)
RP Voltage: -2.0 V to +14.0 V (Note 2 and 3)
Output Short Circuit Current: 100 mA (Note 4)
WARNING:
*Stressing the device beyond the
‘
Absolute Maximum
Ratings
’
may cause permanent damage. These are stress ratings
only. Operation beyond the
‘
Operating Conditions
’
is not recom-
mended and extended exposure beyond the
‘
Operating Conditions
’
may affect device reliability.
NOTES:
1. Operating temperature is for commercial product defined by this
specification.
2. All specified voltages are with respect to GND. Minimum DC volt-
age is -0.5 V on input/output pins and -0.2 V on V
CC
and V
PP
pins.
During transitions, this level may undershoot to -2.0 V for periods
< 20 ns. Maximum DC voltage on input/output pins and V
CC
is V
CC
+ 0.5 V which, during transitions, may overshoot to V
CC
+ 2.0 V for
periods < 20 ns.
3. Maximum DC voltage on V
PP
and RP may overshoot to +14.0 V
for periods <20 ns.
4. Output shorted for no more than one second. No more than one
output shorted at a time.
AC Test Conditions
Figure 10. Transient Input/Output Reference
Waveform for V
CC
= 2.7 V to 3.6 V
Figure 11. Transient Equivalent
Testing Load Circuit
Table 10. Test Configuration
Capacitance Loading Value
TEST CONFIGURATION
V
CC
= 2.7 V to 3.6 V
C
L
(pF)
50
LRS1338A-10
INPUT
0.0
TEST POINTS
OUTPUT
2.7
1.35
1.35
NOTE:
AC test inputs are driven at 2.7 V for a Logic '1' and 0.0 V
for a Logic '0'. Input timing begins and output timing ends
at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.
LRS1338A-11
DEVICE
UNDER
TEST
1N914
OUT
NOTE:
C
L
Includes Jig Capacitance
R
L
= 3.3 k
1.3 V
C
L
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