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參數(shù)資料
| 型號： | LRS1338A |
| 廠商： | Sharp Corporation |
| 英文描述： | Stacked Chip 8M Flash Memory and 2M SRAM |
| 中文描述： | 堆疊芯片800萬快閃記憶體以及2M SRAM |
| 文件頁數(shù)： | 12/36頁 |
| 文件大?。?/td> | 218K |
| 代理商： | LRS1338A |
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LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
12
Data Sheet
READ ARRAY COMMAND
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by writing
the Read Array command. The device remains
enabled for reads until another command is written.
Once the internal WSM has started a block erase or
word write, the device will not recognize the Read Array
command until the WSM completes its operation
unless the WSM is suspended via an Erase Suspend
or Word Write Suspend command. The Read Array
command functions independently of V
PP
voltage and
RP can be V
IH
or V
HH
.
READ IDENTIFIER CODES COMMAND
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the com-
mand write, read cycles from addresses shown in Fig-
ure 5 retrieve the manufacturer and device codes (see
Table 7 for identifier code values). To terminate the
operation, write another valid command. Like the Read
Array command, the Read Identifier Codes command
functions independently of the V
PP
voltage and RP can
be V
IH
or V
HH
. Following the Read Identifier Codes
command, the following information can be read.
READ STATUS REGISTER COMMAND
The status register may be read to determine when
a block erase or word write is complete and whether
the operation completed successfully. It may be read at
any time by writing the Read Status Register com-
mand. After writing this command, all subsequent read
operations output data from the status register until
another valid command is written. The status register
contents are latched on the falling edge of OE or CE,
whichever occurs. OE or CE must toggle to V
IH
before
further reads to update the status register latch. The
Read Status Register command functions indepen-
dently of the V
PP
voltage. RP can be V
IH
or V
HH
.
CLEAR STATUS REGISTER COMMAND
Status register bits SR.5, SR.4, SR.3 or SR.1 are set
to
‘
1
’
s by the WSM and can only be reset by the Clear
Status Register command. These bits indicate various
failure conditions (see Table x). By allowing system
software to reset these bits, several operations (such
as cumulatively erasing multiple blocks or writing sev-
eral words in sequence) may be performed. The status
register may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status Regis-
ter command (50H) is written. It functions indepen-
dently of the applied V
PP
voltage. RP can be V
IH
or
V
HH
. This command is not functional during block
erase or word write suspend modes.
BLOCK ERASE COMMAND
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is first
written, followed by a block erase confirm. This com-
mand sequence requires appropriate sequencing and
an address within the block to be erased (erase
changes all block data to FFFFH). Block precondition-
ing, erase, and verify are handled internally by the
WSM (invisible to the system). After the two-cycle block
erase sequence is written, the device automatically
outputs status register data when read (see Figure 6).
The CPU can detect block erase completion by analyz-
ing the output data of the status register bit SR.7.
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective action. The CUI
remains in read status register mode until a new com-
mand is issued.
This two-step command sequence of set-up fol-
lowed by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to
‘
1
’
. Also, reliable block erasure
can only occur when V
CC
= V
CC1
and V
PP
= V
PPH
. In
the absence of this high voltage, block contents are
protected against erasure. If block erase is attempted
while V
PP
≤
V
PPLK
, SR.3 and SR.5 will be set to
‘
1
’
.
Successful block erase for boot blocks requires that if
set WP = V
IH
or RP = V
HH
. If block erase is attempted
to boot block when the corresponding WP = V
IL
or
RP = V
IH
, SR.1 and SR.5 will be set to
‘
1
’
. Block erase
operations with V
IH
< RP < V
HH
produce spurious
results and should not be attempted.
Table 7. Identifier Codes
CODE
ADDRESS
00000H
00001H
DATA
00B0H
0060H
Manufacture Code
Device Code (Top Boot)
相關PDF資料 |
PDF描述 |
|---|---|
| LRS1341 | Stacked Chip 16M Flash Memory and 2M SRAM |
| LRS1805A | Stacked Chip 64M (x16) Flash Memory + 16M (x16) Smartcombo RAM |
| LRS250 | LIGHT EMITTING DIODES |
| LRS250-DO | LIGHT EMITTING DIODES |
| LRZ180-CO | Array LED 2 mm LED, Diffused |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LRS1341 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Stacked Chip 16M Flash Memory and 2M SRAM |
| LRS1342 | 制造商:Sharp Microelectronics Corporation 功能描述:COMBO 1MX16 FLASH + 128KX16 SRAM 2.7V TO 3.6V 72FBGA - Trays |
| LRS1348 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LRS1360 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LRS1360C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|72PIN|PLASTIC |
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