參數(shù)資料
型號(hào): LRS1338A
廠商: Sharp Corporation
英文描述: Stacked Chip 8M Flash Memory and 2M SRAM
中文描述: 堆疊芯片800萬快閃記憶體以及2M SRAM
文件頁(yè)數(shù): 25/36頁(yè)
文件大?。?/td> 218K
代理商: LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
Data Sheet
25
ALTERNATIVE CE CONTROLLED WRITES
1
V
CC
= 2.7 V to 3.6 V, T
A
= 40
°
C to +85
°
C
NOTES:
1. In systems where CE defines the write pulse width (within a longer WE timing waveform),
all setup, hold, and inactive WE times should be measured relative to the CE waveform.
2. Sampled, not 100% tested.
3. Refer to Table 6 for valid A
IN
and D
IN
for block erase or word write.
4. V
PP
should be held at V
PPH
(and if necessary RP should be held at V
HH
) until
determination of block erase or word write success (SR.1, SR.3, SR.4, SR.5 = 0).
SYMBOL
t
AVAV
t
PHEL
t
WLEL
t
ELEH
t
PHHEH
t
SHEH
t
VPEH
t
AVEH
t
DVEH
t
EHDX
t
EHAX
t
EHWH
t
EHEL
t
EHGL
t
QVVL
t
QVPH
t
QVSL
PARAMETER
MIN.
120
1
0
70
100
100
100
50
50
5
5
0
25
0
0
0
0
MAX.
UNIT
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
Write Cycle Time
RP HIGH Recovery to CE Going LOW
WE Setup to CE Going LOW
CE Pulse Width
RP V
HH
Setup to CE Going HIGH
WP V
IH
Setup to CE Going HIGH
V
PP
Setup to CE Going HIGH
Address Setup to CE Going HIGH
Data Setup to CE Going HIGH
Data Hold from CE HIGH
Address Hold from CE HIGH
WE Hold from CE HIGH
CE Pulse Width HIGH
Write Recovery before Read
V
PP
Hold from Valid SRD HIGH
RP V
HH
Hold from Valid SRD HIGH
WP V
IH
Hold from Valid SRD HIGH
2
2
2
2
3
3
2, 4
2, 4
2, 4
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