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參數(shù)資料
| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 9/128頁(yè) |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Pin Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
9 of 128
April, 2002
190
213
236
3
RXER_1
RXER_2
RXER_3
RXER_4
I
Receive Data Error Input.
These inputs, one per port, indicate
that an external Physical Layer device has detected a symbol
error. This input is clocked in on rising edges of RXC_[1:4]. This
pin is not used in 10 Mbps Serial mode.
194
217
240
7
COL_1
COL_2
COL_3
COL_4
I
Collision Input.
These inputs, one per port, indicate that an
external Physical Layer device has detected a collision between
transmit and receive data.
Management Interface (MI)
170
MDC
O
Management Interface (MI) Clock Output.
This MI clock shifts
serial data in and out of MDIO on rising edges from an external
Physical Layer device.
171
MDIO
I/O
Management Interface (MI) Data I/O.
This bidirectional pin
contains serial data that is clocked in and out on rising edges of
the MDC clock from an external Physical Layer device.
Register Interface
17
ENREGIO
I
Enable Register I/O Operation Input.
This input must be
asserted active low to enable reading and writing of data on the
Register Interface input and output signals. This input is clocked
in on falling edges of WR and RD.
11
WR
I
Write Strobe Input.
This input is a write enable input signal
which has to be asserted active low in order for data to be writ-
ten into the addressed register for a given port.
12
RD
I
Read Strobe Input.
This input is a read enable input signal
which has to be asserted active low in order for data to be read
from the addressed register for a given port. This input must
remain asserted until data is outputted onto CDST[15:0] or until
the READY output is asserted.
15
16
REGPS1
REGPS0
I
Register Port Select Input.
These inputs determine which
port’s 16 REGPS0 registers are being accessed over the Reg-
ister Interface. These inputs are clocked in on falling edges of
WR and RD.
11 = Port 4 Accessed Over Register Interface
10 = Port 3 Accessed Over Register Interface
01 = Port 2 Accessed Over Register Interface
00 = Port 1 Accessed Over Register Interface
Pin Description (Cont.)
Pin #
Pin Name
I/O
Description
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