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參數(shù)資料
| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 15/128頁(yè) |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
15 of 128
April, 2002
3 Functional Description
3.1 General
The L84302 is a quad Ethernet Controller for 100/10 Mbps Ethernet
systems. The L84302 integrates four independent MAC (Media Access
Control) sublayers, as defined in IEEE 802.3. The L84302 has seven
main sections: System Interface, MAC, FIFOs, PHY Interface,
Management Register Interface, and Registers. Each of the sections is
replicated four times, once per port, with the exception of the four
interfaces (System, Register, PHY, and Management), which are
common to all four ports. A top-level block diagram is shown in
Figure 1
,
and a block diagram of each individual port is shown in
Figure 2
.
For each port, The L84302 has a transmit data path and a receive data
path. The transmit data path goes in the System Interface and out the
PHY Interface, as shown in the top half of
Figure 2
. The receive data
path goes in the PHY Interface and out the System Interface, as shown
in the bottom half of
Figure 2
.
On the transmit data path, data for all four ports is input into the System
Interface from an external bus. One port has to be selected, and the data
is then sent to the transmit FIFO of the selected port. The transmit FIFO
provides temporary storage of the data until it is sent to the transmit MAC
section for that port. The transmit MAC takes the data and formats it into
an Ethernet packet per IEEE 802.3 specifications and shown in
Figure 3
.
The Ethernet packet then goes to the PHY Interface for formatting and
transmission to an external PHY chip. There are two PHY Interface
modes on the L84302: MII and 10 Mbps Serial. The data on the PHY
Interface is formatted according to IEEE 802.3 specifications;
Figure 4
shows the formatting. The transmit side manages collisions via the
internal backoff and defer algorithms and also generates MAC Control
Pause frames.
On the receive data path, the PHY Interface receives incoming data from
an external PHY chip for each port. The incoming data must be in either
MII or 10 Mbps Serial format as specified in IEEE 802.3 and shown in
Figure 4
. The PHY Interface converts the data from MII/10 Mbps Serial
format to Ethernet packet data. The Ethernet packet data is then sent to
the receive MAC section for that port. The receive MAC section
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