參數(shù)資料
型號(hào)： L84302
元件分類： 通用總線功能
英文描述： L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述： L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日
文件頁數(shù)： 24/128頁
文件大小： 997K
代理商： L84302
24 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
watermark signal which indicates when the transmit FIFO space has
exceeded the programmable transmit FIFO threshold value. TXRDY_[1:4]
will be asserted or deasserted by the device on rising edges of SCLK,
depending on the fullness of the transmit FIFO. Refer to
Section 3.6,
“Transmit FIFO,” page 37
, for more details on TXRDY_[1:4].
In addition to the TXRDY output, there is also a FIFO space/data
available output indication on the SPDTAVL pin. During a write operation,
the SPDTAVL output is a space available (almost full) indication for the
transmit FIFO and it is asserted active high if there is more than 2 double
words of space available in the transmit FIFO.
TXRET_[1:4] is a transmit packet discard output, one per port.
TXRET_[1:4] is asserted when an error was detected on a transmit
packet. When a transmit error is detected on a packet, the remaining
contents of the packet is flushed from the TX FIFO and TXRET_[1:4] is
latched active high to indicate that the error occurred. TXRET_[1:4] for
the selected port can be cleared by asserting the clearing signal,
CLRTXERR. While TXRET_[1:4] is latched high, the TX FIFO input is
blocked and no data can be loaded into it until it is cleared with
CLRTXERR. See
Section 3.9, “Packet Discard,” page 41
, for more details
on discards and TXRET_[1:4].
TXNOCRC is an input which can disable the internal generation and
appending of the 4 byte CRC value onto the end of the data packet.
TXNOCRC is sampled on rising edges of SCLK and can be asserted on
any SCLK cycle between the first and last double word of a packet to
cause the removal or addition of the CRC to that packet. CRC generation
can also be disabled by setting the transmit CRC disable bit in the
Configuration 1 register. The interaction between the TXNOCRC pin and
CRC disable bit is defined in
Table 4
.
FCNTRL_[1:4] is an input, one per port, which will cause the automatic
generation and transmission of a MAC Control Pause frame in Full
Duplex mode and JAM packet in Half Duplex mode. FCNTRL_[1:4] is
input on rising edges of SCLK. See
Section 3.14, “Flow Control,”
page 51
,
Section 3.15, “Automatic JAM,” page 51
, and
Section 3.16,
“MAC Control Frames,” page 52
, for more details about these features.
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