- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367493 > L84302 L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 PDF資料下載
參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 6/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
6 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
192
215
238
5
RXOVF_1
RXOVF_2
RXOVF_3
RXOVF_4
O
Receive FIFO Overflow Output.
1 = RX FIFO Full
0 = Not Full
These outputs, one per port, are clocked out on rising edges of
the system clock, SCLK.
127
RXTXEOF
I/O
Receive-Transmit End of Frame Input/Output.
This bidirec-
tional pin indicates that the current data word, for the selected
port, is the last double word of the packet. During receive FIFO
reads, this pin is an output and is asserted active high when the
last word of a receive packet is being read out of the receive
FIFO on RXTXDATA[31:0]. During transmit writes, this pin is an
input and needs to be asserted active high when the last word
of the packet is being written into the transmit FIFO on RXTX-
DATA[31:0]. This signal is clocked in/out on rising edges of the
system clock, SCLK.
128
TXNOCRC
I
Transmit No CRC Input.
1 = CRC is not Appended
0 = CRC is Calculated and Appended to Current Transmit
Packet being Input on System Interface
This input is clocked in on rising edges of the system clock,
SCLK, and is for the selected port.
75 76 77
78 81 82
83 84 87
88 89 90
93 94 95
96 102
103 104
105 108
109 110
111 114
115 116
117 120
121 122
123
RXTXDATA[31:0]
I/O
Receive-Transmit Data Input/Output.
This bidirectional bus
contains data read or written to/from the FIFOs for the selected
port. During receive reads, these pins are outputs and contain
data read from the receive FIFO. During transmit reads, these
pins are inputs and contain data to be written to the transmit
FIFO. RXTXDATA[31:0] is clocked in/out on rising edges of the
system clock, SCLK.
Note:
Pin #75 = RXTXDATA 31, Pin #123 = RXTXDATA 0
131
139
147
155
RXABORT_1
RXABORT_2
RXABORT_3
RXABORT_4
I
Receive Abort Input.
1 = Abort Packet, Discard RX FIFO Data, Block RX FIFO Input
Until Start of Next Packet.
0 = No Discard
These inputs, one per port, are clocked in on rising edges of the
system clock, SCLK.
Pin Description (Cont.)
Pin #
Pin Name
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L8560 | Low-Power SLIC with Ringing |
| L8567 | SLIC for Peoples Republic of China Applications |
| L8567-32PLCC | Telecommunication IC |
| L8567-44PLCC | Telecommunication IC |
| L8574D | CAP 15PF 50V 5% C0G SMD-0402 TR-7-PA SN100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L8446-04 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-06 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-07 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-41 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-42 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。