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參數(shù)資料
| 型號(hào)： | L84302 |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 16/128頁(yè) |
| 文件大小： | 997K |
| 代理商： | L84302 |
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April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
decomposes the packet, checks the validity of the packet against certain
error criteria and address filters, and checks for MAC Control frames.
The receive MAC then sends valid packets to the receive FIFO for that
port. The receive FIFO provides temporary storage of data until it is
demanded by the System Interface. The receive FIFOs for all four ports
can be individually selected and accessed by the System Interface. The
System Interface outputs the data for the selected port to an external
bus.
The Register Interface is a separate bidirectional 16-bit data bus through
which configuration inputs can be set and status outputs can be read
from the internal registers and management counters. The internal
register bank is replicated four times, once per port.
The Management Interface, referred to as the MI, is serial interface for
passing data to/from and external PHY.
Each block plus the operating modes are described in more detail in the
following sections.
3.2 Ethernet Frame Format
3.2.1 General
Information in an Ethernet network is transmitted and received in packets
or frames. The basic function of the L84302 is to process Ethernet
frames. An Ethernet frame is defined in IEEE 802.3 and consists of a
preamble, start of frame delimiter (SFD), destination address (DA),
source address (SA) , length/type field (L/T), data, frame check
sequence (FCS), and interpacket gap (IPG). The format for the Ethernet
frame is shown in
Figure 3
.
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