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參數(shù)資料
| 型號(hào)： | L84302 |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 8/128頁(yè) |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
PHY Interface (MII and 10 Mbps Serial)
180
203
226
249
TXC_1
TXC_2
TXC_3
TXC_4
I
Transmit Clock Input.
These inputs, one per port, clock out the
transmit data on TXD[3:0]_[1:4] and TXEN_[1:4] to an external
Physical Layer device on rising edges of this clock in MII mode,
and on falling edges of the clock in 10 Mbps Serial mode.
175
198
221
244
TXEN_1
TXEN_2
TXEN_3
TXEN_4
O
Transmit Enable Output.
These outputs, one per port, are
asserted active high to indicate that data on TXD[3:0] for that
port is valid. These outputs are clocked out on rising edges of
TXC_[1:4] in MII mode and falling edges in 10 Mbps Serial
mode.
176 177
178 179
199 200
201 202
222 223
224 225
245 246
247 248
TXD[3:0]_1
TXD[3:0]_2
TXD[3:0]_3
TXD[3:0]_4
O
Transmit Data Output.
These outputs, one per port, contain
nibble wide transmit data to an external Physical Layer device
and are clocked in on rising edges of TXC_[1:4] in MII Mode. In
10 Mbps Serial mode, only TXD0 is used and data is clocked in
on falling edges of TXC_[1:4].
183
206
229
252
RXC_1
RXC_2
RXC_3
RXC_4
I
Receive Clock Input.
These inputs, one per port, clock in
receive data on RXD[3:0]_[1:4], RXDV_[1:4], and RXER_[1:4]
from an external Physical Layer device on rising edges of this
clock.
193
216
239
6
CRS_1
CRS_2
CRS_3
CRS_4
I
Receive Carrier Sense Input.
These inputs, one per port, have
to be asserted active high to indicate that receive data has been
detected on the Physical Layer device for that port.
191
214
237
4
RXDV_1
RXDV_2
RXDV_3
RXDV_4
I
Receive Data Valid Port 1 Input.
These inputs, one per port,
have to be asserted active high on rising edges of RXC_[1:4] to
indicate when receive data is valid on RXD[3:0]_[1:4]. This pin
is not used in 10 Mbps Serial mode.
187 186
185 184
210 209
208 207
233 232
231 230
256 255
254 253
RXD[3:0]_1
RXD[3:0]_2
RXD[3:0]_3
RXD[3:0]_4
I
Receive Data Port 1 Input.
These inputs, one per port, contain
receive nibble wide receive data from an external Physical Layer
device and are clocked in on rising edges of RXC_[1:4] in MII
mode. In 10 Mbps Serial Mode, only RXD0 is used and data is
clocked out on falling edges of RXC_[1:4].
Pin Description (Cont.)
Pin #
Pin Name
I/O
Description
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