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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 5/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Pin Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
5 of 128
April, 2002
69
70
71
72
RXTXBE3
RXTXBE2
RXTXBE1
RXTXBE0
I/O
Receive-Transmit Byte Enable Input/Output.
These bidirec-
tional signals indicate which bytes of the current 32-bit data
word on RXTXDATA[31:0] contain valid data.
When the device is selected for a transmit FIFO write operation
to a selected port, these pins are configured as inputs and indi-
cate which bytes on RXTXDATA contain valid data.
When the device is selected for a receive FIFO read operation
from a selected port, these pins can be configured to be either
inputs or outputs, depending on how they are programmed via
an internal register bit. If they are configured as inputs, they dic-
tate which bytes the data from the receive FIFO will be read out
on. When configured as outputs, these pins indicated which
bytes contain valid data.
RXTXBE[3:0] is clocked in/out on rising edges of the system
clock SCLK.
133
141
149
157
RXRDY_1
RXRDY_2
RXRDY_3
RXRDY_4
O
Receive FIFO Ready Output.
These outputs, one per port, indi-
cate that either the RX FIFO data has exceeded the
programmable threshold value or an end of a packet was loaded
into the RX FIFO. These outputs are clocked out on rising edges
of the system clock, SCLK, and are put in high impedance state
when RXINTEN is deasserted.
1 = RX FIFO Data >= RXFIFO Threshold
or End Of Frame Loaded Into RX FIFO
0 = Below Threshold
134
142
150
158
TXRDY_1
TXRDY_2
TXRDY_3
TXRDY_4
O
Transmit FIFO Ready Output.
These outputs, one per port,
indicate that the TX FIFO space exceeds the programmable
threshold value. These outputs are clocked out on rising edges
of the system clock, SCLK, and are put in high impedance state
when TXINTEN is deasserted.
1 = TX FIFO Space >= TX FIFO Threshold
0 = Below Threshold
126
SPDTAVL
O
FIFO Space/Data Available Output.
For RX FIFO Reads:
1 = More than 1 Double Word of Data in RX FIFO
0 = Data Not Available
For TX FIFO Writes:
1 = More than 2 Double Words of TX FIFO Space Available
0 = Space Not Available
This output is clocked out on rising edges of the system clock,
SCLK, and is for the selected port.
Pin Description (Cont.)
Pin #
Pin Name
I/O
Description
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