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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數(shù)： | 38/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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38 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
space exceeds or equals the programmable threshold associated with
the watermark.
The transmit watermark threshold for TXRDY can be programmed over
the entire 128-byte TX FIFO range. The watermark threshold can be
programmed with four bits that reside in the FIFO Threshold register.
Once the space in the FIFO exceeds or equals the threshold of the
watermark, then the watermark output pin TXRDY is asserted active low.
The watermark stays asserted until the space in the FIFO goes below
the threshold.
Normally, the TXRDY watermark is asserted/deasserted when the FIFO
space goes below/above the TX FIFO threshold, respectively. TXRDY
can be configured to deassert when either the threshold limit is exceeded
or an EOF is written to the TX FIFO by setting the TXRDY function select
bit in the Configuration 2 register. When this bit is set, TXRDY will remain
deasserted until the packet in the TX FIFO has been completely
transmitted out of the TX FIFO.
3.6.4 Almost Full Indication
There is an almost full output indication for the transmit FIFO on the
SPDTAVL pin. When a TX FIFO write operation is in progress, the
SPDTAVL output pin will be asserted active low if there is less than 3
double words of TX FIFO space available in the transmit FIFO.
3.6.5 TX Underflow
The transmit FIFO underflow condition occurs when the TX FIFO is
empty but the MAC still is requesting data to complete the transmission
of a packet. If the transmit FIFO underflows, then (1) TXRET is asserted
and latched, (2) packet transmission to the MII is halted with TXEN being
deasserted, (3) all input data to the TX FIFO is blocked until the TXRET
signal is cleared with CLRERR. Refer to
Section 3.9, “Packet Discard,”
page 41
, for more information about discards.
3.6.6 Discards
Certain error conditions detected for a given packet will cause the data
for that packet to be discarded or flushed from the TX FIFO. Packet
discards are described in more detail in
Section 3.9, “Packet Discard,”
page 41
.
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