參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊,4月2日
文件頁數(shù): 75/128頁
文件大小: 997K
代理商: L84302
Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
75 of 128
April, 2002
Bit 0 occurs on CDST0/CDST8 pin
Bit 0 occurs on CDST0/CDST8 pin
Table 19
Hash Filter 0-7 Register Definition
7
6
5
4
3
2
1
0
F7
R/W
F6
R/W
F5
R/W
F4
R/W
F3
R/W
F2
R/W
F1
R/W
F0
R/W
Bit
Symbol
Name
Definition
R/W
Def.
7
6
5
4
3
2
1
0
F7
F6
F5
F4
F3
F2
F1
F0
Hash Filter
These eight registers contain 64-bits that are
used by the receive hash filter. The receive
hash filter is used for filtering the Destination
Address on multicast packets. Refer to the
Multicast Address Filter section for more
details about the hash filter function and what
these bits represent.
R/W
0
Table 20
Transmit Defer Register Definition
7
6
5
4
3
2
1
0
DEFER7
R/W
DEFER6
R/W
DEFER5
R/W
DEFER4
R/W
DEFER3
R/W
DEFER2
R/W
DEFER1
R/W
DEFER0
R/W
Bit
Symbol
Name
Definition
R/W
Def.
7
6
5
4
3
2
1
0
DEFER7
DEFER6
DEFER5
DEFER4
DEFER3
DEFER2
DEFER1
DEFER0
This register contains an 8-bit number that is
used by the Transmit MAC to calculate the
minimum interpacket gap. Refer to
Section 3.4.5, “Interpacket Gap,” page 29
, for
more details. Bit 0 is the LSB.
R/W
0
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