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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數(shù)： | 67/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
67 of 128
April, 2002
described in more detail in
Section 3.19.5, “Interrupt,” page 67
. The bit
type definitions are summarized in
Table 13
.
3.19.5 Interrupt
An interrupt is triggered when certain output status bits are set. These
bits are called interrupt bits and are designated as R/LHI bits as
described in the previous section. When R/LHI or interrupt bits are set
high, they stay latched high until read and the interrupt pin for that port
is asserted. When interrupt bits are read, they are cleared low and the
interrupt pin for that port is deasserted (provided there are no other
interrupt bits set. All of the interrupt bits can be enabled or disabled,
some individually. Disabling (also referred to as masking) an interrupt bit
prevents that interrupt bit from causing an interrupt for that port.
Table 14
lists all the bits that assert interrupt and their associated disable/mask
bits.
Table 13
Register Bit Type Definition
Sym.
Name
Definition
Write Cycle
Read Cycle
W
Write
Input
No Operation, 0’s
R
Read
No Operation, Hi Z
Output
R/W
Read/Write
Input
Output
R/LH
Read/Latching High
No Operation, Hi Z
Output
When bit goes high, bit latched. When bit
is read, bit updated.
R/LHI
Read/Latching High with
Interrupt
No Operation, Hi Z
Output
When bit goes high, bit latched and inter-
rupt asserted (if not masked). When bit is
read, bit updated and interrupt cleared.
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