參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術手冊,4月2日
文件頁數(shù): 72/128頁
文件大小: 997K
代理商: L84302
72 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
Bit 0 occurs on CDST0/CDST8 pin
Table 16
Station Address 0-5 Register Definition
7
6
5
4
3
2
1
0
A7
R/W
A6
R/W
A5
R/W
A4
R/W
A3
R/W
A2
R/W
A1
R/W
A0
R/W
Bit
Symbol
Name
Definition
R/W
Def.
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Station Address
These six registers contain the 48-Bit MAC
Station Address.
A0 in Station Address 0 Register corresponds
to the first MAC address bit received in the
data stream on the System Interface (shown
as DA[0] in
Figure 4
); A7 in Station Address 5
Register corresponds to the last address bit
received 0.
The Station Address is used for (1) receive
unicast address matching against the incom-
ing DA, and (2) automatic MAC Control Pause
frame generation.
R/W
0
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