參數(shù)資料
型號(hào)： L84302
元件分類： 通用總線功能
英文描述： L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述： L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日
文件頁數(shù)： 66/128頁
文件大?。?/td> 997K
代理商： L84302
66 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
3.19.3 Bus Width
The bus width of the Register Interface can be selected to be either 8 or
16-bits wide by appropriately setting the BUSSIZE pin.
When the bus width is set to 8-bits wide (BUSSIZE=0), all registers have
a unique address as determined by the A[7:0] pins, as shown in
Table 15
. To read out the 32-bit counter result over the 8-bit Register
Interface bus, four successive reads on the same address will have to be
done to output all 4 bytes of the 32-bit result. The first 8-bit word that is
read out contains the upper 8 bits of the counter result (MS byte), and
the fourth 8-bit word contains the lowest 8 bits (LS byte). Note that when
the bus width is set to 8 bits, the byte enables inputs on BE[3:0] are
ignored.
When the bus width is set to 16 bits (BUSSIZE=1), the address pin A0
is ignored, and all registers have a unique address determined by A[7:1],
as shown in
Table 15
. To read out the 32-bit counter result over the 16-
bit Register Interface bus, two successive reads on the same address
are required to output the two double words of the 32-bit result. The first
16-bit word that is read out contains the upper 16 bits of the counter
result (MS word), and the last 16-bit word contains the lower 16 bits (LS
word). Note that when the bus width is set to 16 bits, the A0 address
input is ignored.
The Byte Enable pins, BE[1:0], control which byte of the 16-bit word is
accessed when the Register Interface is configured for 16-bit bus width.
The Byte Enable pins are ignored when the Register Interface is
configured to be 8 bits.
3.19.4 Bit Types
The Register Interface is bidirectional, and there are many types of bits
in the registers. Write bits (W) are inputs during a write cycle and are
logic 0 during a read cycle. Read bits (R) are outputs during a read cycle;
during a write cycle they are high impedance and are ignored.
Read/Write bits (R/W) are actually write bits that can be read out during
a read cycle. R/LH bits are read bits that latch themselves when they go
high, and they stay latched high until read. After they are read, they are
cleared low. R/LHI bits are the same as R/LH bits except that they also
assert interrupt when they latch high. Some of the R/LHI bits can also
be programmed to not assert, or mask, the interrupt function. This is
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