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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 57/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
57 of 128
April, 2002
A complete list of the counters along with their definitions is shown in
Table 12
. The exact correspondence of the actual MIB objects from the
above IETF and IEEE specifications to the actual L84302 counters
locations is described in
Section 4, “Application Information,” page 92
,
and is shown there in
Table 38
through
Table 41
.
The current count for each counter is stored in individual Counter
Registers. The address location for each Counter Register is also shown
in
Table 12
. Note that all the counters are 32 bits long, but the Counter
Register length is only 16 bits. The entire 32 bits can be read out of the
device by doing two successive 16-bit reads from the same address (or
four reads, if BUSSIZE is set for 8-bit bus width). The first 16-bit read
outputs the upper 16 bits (MS byte), the second 16-bit word outputs the
lower 16 bits (LS byte).
Each counter is responsible for tabulating the number of times a specific
event occurs. When a counter is read out, the count can be automatically
reset to 0 or it can remain unchanged (programmable). Counters can be
configured to either stop counting when they reach their maximum count
or rollover (programmable). When a counter read operation is initiated,
the 32-bit counter result to be accessed is transferred to two internal 16-
bit holding registers. These holding registers freeze and store the counter
result for the duration of the read operation while allowing the internal
counter to continue to increment if needed.
3.18.2 Counter Overflow
Each 32-bit counter has a status output bit associated with that counter.
The status output bits are stored in the Counter Status 0-6 registers.
These status bits are set when the counter value reaches 80000000
H
(i.e., MSB bit goes from a 0 to a 1). Thus, the status bits are set when
the counter becomes half full.
The counter status bits stay latched high until they read out (R/LHI bits).
When a counter status bit is read out, it is then cleared low. Counter
status bits are also interrupt bits; that is, the setting of any counter status
bit will cause the assertion of the interrupt pin, INT_[1:4] for that port.
When a counter status bit is read, the interrupt caused by that bit is
cleared. Note that INT_[1:4] stays asserted until all interrupt bits are
cleared. Each counter status bit can be individually programmed to not
assert interrupt by setting the mask bit associated with that counter bit
in Counter Interrupt Enable 1-7 registers.
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