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參數(shù)資料
| 型號(hào)： | L80227 |
| 廠商： | LSI CORP |
| 元件分類(lèi)： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁(yè)數(shù)： | 95/158頁(yè) |
| 文件大小： | 1084K |
| 代理商： | L80227 |
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Draft 6/5/00
Frame Structure
5-5
Copyright 1999 by LSI Logic Corporation. All rights reserved.
5.3 Frame Structure
The structure of the serial port frame is shown in
Figure 5.2
and a timing
diagram is shown in
Figure 5.1
. Each serial port access cycle consists
of 32 bits (or 144 bits if multiple register access is enabled and
REGAD[4:0] = 0b11111), exclusive of idle. The first 16 bits of the serial
port cycle are always write bits and are used for control and addressing.
The last 16 bits are data that is written to or read from a data register.
The first two bits in
Figure 5.2
and
Figure 5.1
are start bits (ST[1:0]) and
must be written as a 0b01 for the serial port cycle to continue. The next
two bits are the READ and WRITE bits, which determine whether the
registers are being read or written. The next five bits are the PHY device
address bits (PHYAD[4:0]), and they must match the inverted values
latched from the MDA[4:0]n pins during the power on reset time for
access to continue.
The next five bits are register address select (REGAD[4:0]) bits, which
select one of the eight registers for access. The next two bits are
turnaround (TA) bits, which are not actual register bits but provide the
device extra time to switch the MDIO pin function from a write pin to a
read pin, if necessary. The final 16 bits of the MI serial port cycle are
written to or read from the specific data register that the register address
bits (REGAD[4:0]) designate.
Figure 5.2
shows the MI frame structure.
IDLE
Idle Pattern
These bits are an idle pattern. The device does not
initiate an MI cycle until it detects an idle pattern of at
least 32 consecutive ones.
W
ST[1:0]
Start Bits
When ST[1:0] = 01, a MI serial port access cycle starts.
W
READ
Read Select
When the READ bit is 1, it designates a read cycle.
W
Figure 5.2
MI Serial Frame Structure
IDLE
ST[1:0]
READ
WRITE
PHYAD[4:0]
REGAD[4:0]
TA[1:0]
D[15:0]
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| L8050HPLT1 | General Purpose Transistors NPN Silicon |
| L8050HPLT1G | General Purpose Transistors NPN Silicon |
| L8050HQLT1 | General Purpose Transistors NPN Silicon |
| L8050HQLT1G | General Purpose Transistors NPN Silicon |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80227/B | 制造商:LSI Corporation 功能描述: 制造商:LSI Corporation 功能描述:L80227/B |
| L80227/BI | 制造商:LSI Corporation 功能描述:L80227/BI |
| L80227FR | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, two |
| L80227-I | 制造商:LSI Corporation 功能描述:STD CELL ASIC |
| L80227-I-LEADFREE | 制造商:LSI Corporation 功能描述:796000124413 |
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