參數(shù)資料
型號(hào): L80227
廠商: LSI CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝: LQFP-64
文件頁數(shù): 65/158頁
文件大?。?/td> 1084K
代理商: L80227
Draft 6/5/00
Controller Interface Signals (MII)
3-3
Copyright 1999 by LSI Logic Corporation. All rights reserved.
TPI+
Twisted-Pair Receive Input (Positive)
The TPI+ pin functions as the positive signal in the
twisted-pair input.
I
TPI-
Twisted-Pair Receive Input (Negative)
The TPI- pin functions as the negative signal in the
twisted-pair input.
I
3.2 Controller Interface Signals (MII)
CRS
Carrier Sense Output
The CRS output is asserted HIGH when valid data is
detected on the receive TP inputs. CRS is clocked out on
the falling edge of RX_CLK.
O
OSCIN
Clock Oscillator Input
There must be either a 25 MHz crystal between this pin
and GND or a 25 MHz clock applied to this pin. TX_CLK
output is generated from this input.
I
RX_CLK
Receive Clock Output
Receive data on RXD, RX_DV, and RX_ER is clocked out
to an external controller on the falling edge of RX_CLK.
O
RXD[3:0]
Receive Data Output
RXD[3:0] contain receive nibble data from the TP input,
and they are clocked out on the falling edge of RX_CLK.
O
RX_DV
Receive Data Valid Output
RX_DV is asserted HIGH when valid decoded data is
present on the RXD outputs. RX_DV is clocked out on the
falling edge of RX_CLK.
O
RX_EN
Receive Enable Input
When RX_EN is HIGH, all of the receive outputs
(RX_CLK, RXD[3:0], RX_DV, RX_ER, COL) are enabled.
I
When RX_EN is LOW, the outputs are in a
high-impedance state.
RXER
Receive Error Output
RXER is asserted HIGH when a coding error or other
specified errors are detected on the receive twisted-pair
inputs. The signal is clocked out on the falling edge of
RX_CLK.
O
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