參數(shù)資料
型號(hào): L80227
廠商: LSI CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器)
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝: LQFP-64
文件頁數(shù): 29/158頁
文件大?。?/td> 1084K
代理商: L80227
Draft 6/5/00
Block Diagram Description
2-9
Copyright 1999 by LSI Logic Corporation. All rights reserved.
2.3.2 Controller Interface
This section describes the controller interface operation.
2.3.2.1 High Impedance Control
When the RX_EN pin is LOW, the following controller interface outputs
are placed in the high impedance state:
RX_CLK
RXD[3:0]
RX_DV
RX_ER
COL
2.3.2.2 MII Interface
The device has an MII interface to an external Ethernet Media Access
Controller (MAC).
MII (100 Mbits/s) –
The MII is a nibble wide packet data interface
defined in IEEE 802.3 and shown in
Figure 2.3
. The L80227 meets all
the MII requirements outlined in IEEE 802.3. The L80227 can directly
connect, without any external logic, to any Ethernet controller or other
device that also complies with the IEEE 802.3 MII specifications.
The MII interface contains the following signals:
Transmit data bits (TXD[3:0])
Transmit clock (TX_CLK)
Transmit enable (TX_EN)
Transmit error (TX_ER)
Receive data bits (RXD[3:0])
Receive clock (RX_CLK)
Carrier sense (CRS)
Receive data valid (RX_DV)
Receive data error (RX_ER)
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