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參數(shù)資料
| 型號： | L80227 |
| 廠商： | LSI CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX 以太網(wǎng)物理層處理器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁數(shù)： | 32/158頁 |
| 文件大小： | 1084K |
| 代理商： | L80227 |
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Draft 6/5/00
2-12
Functional Description
Copyright 1999 by LSI Logic Corporation. All rights reserved.
RX_CLK for the duration of that RX_CLK clock cycle during which the
nibble containing the error is output on RXD[3:0].
The collision output, COL, is asserted whenever the collision condition is
detected.
MII (10 Mbits/s) –
MII 10 Mbits/s operation is identical to 100 Mbits/s
operation except:
The TX_CLK and RX_CLK clock frequency is reduced to 2.5 MHz
TX_ER is ignored
RX_ER is disabled and always held LOW
Receive operation is modified as follows:
On the receive side, when the squelch circuit determines that invalid
data is present on the TP inputs, the receiver is idle. During idle,
RX_CLK follows TX_CLK, RXD[3:0] is held LOW, and CRS and
RX_DV are deasserted. When a start of packet is detected on the
TP receive inputs, CRS is asserted and the clock recovery process
starts on the incoming TP input data. After the receive clock has
been recovered from the data, the RX_CLK is switched over to the
recovered clock and the data valid signal RX_DV is asserted on a
falling edge of RX_CLK. Once RX_DV is asserted, valid data is
clocked out on RXD[3:0] on the falling edge of RX_CLK. The
RXD[3:0] data has the same packet structure as the TXD[3:0] data
and is formatted on RXD[3:0] as specified in IEEE 802.3 and shown
in
Figure 2.3
. When the end of packet is detected, CRS and RX_DV
are deasserted. CRS and RX_DV also stay deasserted as long as
the device is in the Link Fail State.
MII Disable –
To disable the MII inputs and outputs, set the MII_DIS bit
in the MI serial port Control register. When the MII is disabled, the MII
inputs are ignored, and the MII and TP outputs are placed in a high-
impedance state.
If the MI address lines, MDA[3:0]n, are pulled HIGH during reset or
powerup, the L80227 powers up and resets with the MII disabled.
Otherwise, the L80227 powers up and resets with the MII enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80227/B | 制造商:LSI Corporation 功能描述: 制造商:LSI Corporation 功能描述:L80227/B |
| L80227/BI | 制造商:LSI Corporation 功能描述:L80227/BI |
| L80227FR | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, two |
| L80227-I | 制造商:LSI Corporation 功能描述:STD CELL ASIC |
| L80227-I-LEADFREE | 制造商:LSI Corporation 功能描述:796000124413 |
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