Host Interface Registers
4-3
First Slice Start Code Detect Interrupt
This bit is set when the decoder detects the first slice
start code after the picture layer. INTRn is asserted
unless the host sets the mask bit.
2
Sequence End Code Detect Interrupt
This bit is set when the decoder detects a sequence end
code. INTRn is asserted unless the host sets the mask
bit.
3
SDRAM Transfer Done Interrupt
This bit is set when an SDRAM block move is completed.
INTRn is asserted unless the host sets the mask bit.
4
Reserved
5
Set this bit when writing to Register 0.
Audio Sync Recovery Interrupt
The audio sync recovery bit is set when sync is re-
established after any errors, i.e., when three good frames
are detected after synchronization was lost.
6
This bit is cleared when read. INTRn is also asserted
unless the host sets the mask bit.
New Field Interrupt
7
This bit is set after a short delay after the termination of
the Vertical Sync pulse from the PAL/NTSC Encoder.
INTRn is also asserted unless the host sets the mask bit.
Figure 4.2
Register 1 (0x001)
Audio Sync Code Detect Interrupt
This bit is set when the Audio Decoder detects a valid
audio sync code. The interrupt is intended to be used for
synchronization of presentation units. This is achieved by
sampling the System Clock Reference (SCR) using the
capture register function of the SCR. Also at this time, the
0
7
6
5
4
3
2
1
0
Read
SCR
Compare
Interrupt
SCR
Overflow
Interrupt
Begin
Vertical
Blank
Interrupt
Begin Active
Video
Interrupt
Reserved
SCR
Compare
Audio
Interrupt
Picture Start
Code Detect
Interrupt
Audio Sync
Code Detect
Interrupt
Write
SCR
Compare
Mask
SCR
Overflow
Mask
Begin
Vertical
Blank Mask
Begin Active
Video Mask
Reserved
SCR
Compare
Audio Mask
Picture Start
Code Detect
Mask
Audio Sync
Code Detect
Mask