Video Decoder Registers
4-21
Figure 4.22
Register 69 (0x045)
Enable Video Read Compare DTS
When this bit is set, the Video ES channel buffer read
pointer is compared with the Video ES Channel Buffer
Compare DTS Address written in Registers 108, 109,
and 110 (
page 4-27
) by the host. When the two
addresses match, the DTS Video Event Interrupt bit
(Register 2, bit 7,
page 4-6
) is set and an interrupt is
generated, if not masked, by asserting the INTRn output
signal. This can be used as an aid to audio/video
synchronization by the host software. When INTRn is
asserted, the host should read Registers 0 through 4 to
determine the cause of the interrupt, take the necessary
action, and deassert INTRn by setting the Clear Interrupt
Pin bit (Register 6, bit 0,
page 4-10
).
R/W 0
Enable Audio Read Compare DTS [1:0]
The bit encoding and meanings are shown in the
following table.
R/W [2:1]
When these bits are configured for a compare, the
selected Audio ES channel buffer read pointer is
compared with the Audio ES Channel Buffer Compare
DTS Address written in Registers 111, 112, and 113
(
page 4-28
) by the host. When the two addresses match,
the DTS Audio Event Interrupt bit (Register 2, bit 6,
page 4-6
) is set and an interrupt is generated, if not
masked, by asserting the INTRn output signal. This can
be used as an aid to audio/video synchronization by the
host software.
7
5
4
3
2
1
0
Reserved
Video Numitems/Pics Panic
Mode Select
Enable Audio Read
Compare DTS
Enable Video
Read Compare
DTS
Bits
Description
0b00
0b01
0b10
0b11
Disable compare
Audio decoder read pointer compare
IEC958 (S/P DIF) read pointer compare
Reserved