Audio Decoder Registers
4-85
User
R/W 6
The value of the User bit to be packed in the IEC958
(S/P DIF) output. The default is 0.
Valid
R/W 7
The data Valid bit to be packed in the IEC958 (S/P DIF)
output. The bit is set when the S/P DIF output is from a
formatter in the Audio Decoder and is cleared when the
output is from one of the audio decoders.
Figure 4.128 Register 364 (0x16C)
ACLK Divider Select [3:0]
R/W [3:0]
The host sets these bits to select clock divider values
which derive the S/P DIF interface BCLK, DAC interface
BCLK, and external DAC A_ACLK from the selected
ACLK_ input (bits 0 and 1 in Register 363). The divider
values depend on ACLK_ availability, the input audio
sampling frequency (Fs), the sample resolution
(16/24/32 bits per sample), and the external DAC
capabilities. The L64105 supports sampling rates of 32,
44.1, and 48 kHz for MPEG, and 48 and 96 kHz for
Linear PCM. The equations for the derived clocks are:
S/P DIF BCLK = Fs * 32 bits per sample * 2 channels * 2
marks = Fs * 128
DAC BCLK
= Fs * 32 bits per sample * 2 channels
= Fs * 64
Ext DAC A_ACLK
= Fs * 32 bits per sample * K
= Fs * 256 or Fs * 384
The available divider settings are listed in
Table 4.4
. Use
the following cases as selection criteria:
Case I: All of the ACLK_ inputs are available. Select
the ACLK_ which is a multiple of the input sampling
frequency using bits 0 and 1 in Register 363. Then
use the 0x0 through 0x4 ACLK Divider Select code
that matches the Fs-multiple of the ACLK_. For
example, if the input sampling frequency is 32 kHz
and ACLK_32 = 512 * 32 kHz, use the 0x2 ACLK
Divider Select code.
7
5
4
3
0
Reserved
LPCM - Dynamic
Range On
ACLK Divider Select [3:0]