Index
IX-33
Vline count init bit
4-66
usage overview
9-12
voltage
11-3
output
11-4
VREQn signal
2-5
asynchronous transfers
6-4
,
6-5
channel bypass and
6-8
description
2-5
synchronous transfers and
6-7
VREQn status bit
4-10
VS signal
2-9
See also vertical sync
description
2-9
usage overview
9-5
,
9-10
VSYNC input type bit
4-68
usage overview
9-10
VSYNC signal
7-8
VVALIDn signal
2-6
AC timing
11-14
asynchronous transfers
6-4
description
2-6
input synchronization circuit
6-6
synchronous transfers
6-5
constraints
6-6
timing
11-15
transport streams and
6-25
W
WAITn signal
2-4
description
2-4
waits
4-89
,
10-24
wide images
9-32
word offset
4-66
,
9-34
write pointers
1-3
audio ES channel buffer
10-7
,
10-8
reset
4-20
audio PES header/system channel buffer reset
4-20
auxiliary data
8-21
buffer start
6-28
current address
audio ES channel buffer
4-26
audio PES header/system channel buffer
4-29
video ES channel buffer
4-26
video PES header channel buffer
4-27
elementary stream mode
6-14
external SDRAM
6-27
PES packets
6-15
transport streams
6-25
user data
8-24
video ES channel reset
4-20
video PES header channel buffer reset
4-20
WRITEn signal
2-3
description
2-3
writes
asynchronous channel timing
11-14
audio PES header/system channel
buffer
6-10
,
6-11
,
6-12
channel bypass enable
4-10
contiguous OSD storage
9-28
direct
4-17
DMA controller
5-16
,
5-17
starting addresses
4-46
external OSD mode
9-32
FIFO
1-3
FIFO status
4-38
host
2-3
,
4-41
host flowchart
5-13
Intel mode timing
5-5
Intel mode timing diagram
11-13
Motorola mode timing
5-3
Motorola mode timing diagram
11-10
off-chip memory
6-9
OSD palette
4-60
PCM samples
4-83
,
10-6
SDRAM
4-47
,
5-10
to
5-13
,
7-2
,
9-23
starting addresses
4-42
SDRAM cycle enable
2-8
SDRAM timing cycle
7-5
SDRAM timing diagram
11-8
synchronous
2-6
video PES header channel buffer
6-11
Y
Y[5:0] bits
9-27
Y-B color difference
9-28
YCbCr
B-9
YCbCr values
4-60
,
9-30
Y-R color difference
9-28
YUV
B-9
Z
zigzag ordering
A-4
ZTEST signal
2-12
description
2-12