
Arch
18 Wed May 28 17:36:23 1997
Draft 1/21/97
2-18
Architecture
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
ACTIVE - This 1-bit eld is used for enabling or disabling the PID value.
When reset to 0, the PID is not active; when set to 1, the PID is in active
mode.
2.3.2
PID Post-
Processor
The PID Post-processor is responsible for the next level of the PID lter-
ing of transport packets. The pre-processing block transfers those trans-
port packets that pass the PID matching process on to the PID Post-
processor. The PID Post-processor processes the transport packet
according to the Attribute Control Register File (ACRF) and the match
and mask registers during the post-processing operation. The PID Post-
processor uses some ACRF elds to store the results temporarily while
switching from one PID to the next. For example, when ltering sections
of different PIDs, the PID Post-processor stores the CRC32 and section
length of all the PIDs in process. The ACRF and match and mask regis-
ters are write-only. Reading them during processing can corrupt the l-
tering process.
cards transport packets whose TEI ag was set HIGH. It is assumed that
packets in this block are free of data errors, so the TEI ag is not pro-
cessed. However, the block checks for stream-level errors from the fol-
lowing sources:
Packet Lost Error (Discontinuity)
CRC32 Error (Discontinuity in PSI)
2.3.2.1 Packet Integrity Check
The PID Post-processor performs packet integrity check to conrm the
integrity of packets for each active PID. The transport header contains a
4-bit Continuity Counter (CC) eld. That is derived to let the transport
demultiplexer check the validity of the packet arriving at the L64007. The
transport format dictates that adjacent packets for the same PID have a
CC value sequentially incremented by one (exceptions are described
below). If this rule is violated, a discontinuity condition is triggered in the
transport format dictates that if there is a discontinuity, the CC mismatch